AM28F256A_95 查看數據表（PDF） - Advanced Micro Devices

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AM28F256A_95

256 Kilobit (32,768 x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms

Advanced Micro Devices 

AMD

ERASE, PROGRAM, AND READ MODE

VPP = 12.0 V ± 5%

Command Register Active

Write Operations

High voltage must be applied to the VPP pin in order to

activate the command register. Data written to the regis-

ter serves as input to the internal state machine. The

output of the state machine determines the operational

function of the device.

The command register does not occupy an addressable

memory location. The register is a latch that stores the

command, along with the address and data information

needed to execute the command. The register is written

by bringing WE and CE to VIL, while OE is at VIH. Ad-

dresses are latched on the falling edge of WE, while

data is latched on the rising edge of the WE pulse. Stan-

dard microprocessor write timings are used.

The device requires the OE pin to be VIH for write opera-

tions. This condition eliminates the possibility for bus

contention during programming operations. In order to

write, OE must be VIH, and CE and WE must be VIL. If

any pin is not in the correct state a write command will

not be executed.

Refer to AC Write Characteristics and the Erase/Pro-

gramming Waveforms for specific timing parameters.

Command Definitions

The contents of the command register default to 00H

(Read Mode) in the absence of high voltage applied to

the VPP pin. The device operates as a read only mem-

ory. High voltage on the VPP pin enables the command

register. Device operations are selected by writing spe-

cific data codes into the command register. Table 3

defines these register commands.

Read Command

Memory contents can be accessed via the read com-

mand when VPP is high. To read from the device, write

00H into the command register. Standard microproces-

sor read cycles access data from the memory. The

device will remain in the read mode until the command

register contents are altered.

The command register defaults to 00H (read mode)

upon VPP power-up. The 00H (Read Mode) register de-

fault helps ensure that inadvertent alteration of the

memory contents does not occur during the VPP power

transition. Refer to the AC Read Characteristics and

Waveforms for the specific timing parameters.

Table 3. Am28F256A Command Definitions

Command

Read Memory (Note 4)

Read Auto select

Embedded Erase Set-up/

Embedded Erase

Embedded Program Set-up/

Embedded Program

Reset (Note 4)

First Bus Cycle

Operation

(Note 1)

Address

(Note 2)

Write

X

Write

X

Write

X

Data

(Note 3)

00H/FFH

80H or 90H

30H

Second Bus Cycle

Operation

(Note 1)

Address

(Note 2)

Read

RA

Read

00H/01H

Write

X

Write

X

10H or 50H Write

PA

Write

X

00H/FFH

Write

X

Notes:

1. Bus operations are defined in Table 1.

2. RA = Address of the memory location to be read.

PA = Address of the memory location to be programmed.

Addresses are latched on the falling edge of the WE pulse.

X = Don’t care.

3. RD = Data read from location RA during read operation.

PD = Data to be programmed at location PA. Data latched on the rising edge of WE.

4. Please reference Reset Command section.

Data

(Note 3)

RD

01H/2FH

30H

PD

00H/FFH

2-44

Am28F256A

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