AM28F256A_95 查看數據表（PDF） - Advanced Micro Devices

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AM28F256A_95

256 Kilobit (32,768 x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms

Advanced Micro Devices 

temperature is accomplished in 1.5 seconds, including

preprogramming.

AMD’s Am28F256A is entirely pin and software

compatible with AMD’s Am28F020A, Am28F010A and

Am28F512A Flash memories.

Embedded Programming Algorithm vs.

Flashrite Programming Algorithm

The Flashrite Programming algorithm requires the user

to write a program set-up command, a program com-

mand (program data and address), and a program verify

command followed by a read and compare operation.

The user is required to time the programming pulse

width in order to issue the program verify command. An

integrated stop timer prevents any possibility of over-

programming. Upon completion of this sequence the

data is read back from the device and compared by the

user with the data intended to be written; if there is not a

match, the sequence is repeated until there is a match or

the sequence has been repeated 25 times.

AMD’s Embedded Programming algorithm requires the

user to only write a program set-up command and a pro-

gram command (program data and address). The

device automatically times the programming pulse

width, provides the program verify and counts the

number of sequences. A status bit, Data Polling, pro-

vides feedback to the user as to the status of the

programming operation.

Embedded Erase Algorithm vs. Flasherase Erase

Algorithm

The Flasherase Erase algorithm requires the device to

be completely programmed prior to executing an erase

command. To invoke the erase operation the user writes

an erase set-up command, an erase command, and an

erase verify command. The user is required to time the

erase pulse width in order to issue the erase verify

AMD

command. An integrated stop timer prevents any possi-

bility of overerasure. Upon completion of this sequence

the data is read back from the device and compared by

the user with erased data. If there is not a match, the

sequence is repeated until there is a match or the

sequence has been repeated 1,000 times.

AMD’s Embedded Erase algorithm requires the user to

only write an erase set-up command and erase com-

mand. The device will automatically pre-program and

verify the entire array. Then the device automatically

times the erase pulse width, provides the erase verify

and counts the number of sequences. A status bit, Data

Polling, provides feedback to the user as to the status of

the erase operation.

Commands are written to the command register using

standard microprocessor write timings. Register con-

tents serve as inputs to an internal state-machine which

controls the erase and programming circuitry. During

write cycles, the command register internally latches ad-

dress and data needed for the programming and erase

operations. For system design simplification, the

Am28F256A is designed to support either WE or CE

controlled writes. During a system write cycle, ad-

dresses are latched on the falling edge of WE or CE

whichever occurs last. Data is latched on the rising edge

of WE or CE whichever occurs first. To simplify the fol-

lowing discussion, the WE pin is used as the write cycle

control pin throughout the rest of this text. All setup and

hold times are with respect to the WE signal.

AMD’s Flash technology combines years of EPROM

and EEPROM experience to produce the highest levels

of quality, reliability, and cost effectiveness. The

Am28F256A electrically erases all bits simultaneously

using Fowler-Nordheim tunneling. The bytes are pro-

grammed one byte at a time using the EPROM program-

ming mechanism of hot electron injection.

Am28F256A

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