HEF4020B 查看數據表（PDF） - NXP Semiconductors.
零件编号
产品描述 (功能)
生产厂家
HEF4020B Datasheet PDF : 13 Pages
| |||
NXP Semiconductors
HEF4020B
14-stage binary counter
CP input
MR input
Q0
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Fig 6. Timing diagram
1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384
001aad726
8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
VDD
IIK
VI
IOK
II/O
IDD
Tstg
Tamb
Ptot
supply voltage
input clamping current
input voltage
output clamping current
input/output current
supply current
storage temperature
ambient temperature
total power dissipation
VI < 0.5 V or VI > VDD + 0.5 V
VO < 0.5 V or VO > VDD + 0.5 V
Tamb −40 °C to +85 °C
DIP16 package
SO16 package
P
power dissipation
per output
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C.
Min
−0.5
-
−0.5
-
-
-
−65
−40
[1] -
[2] -
-
Max
Unit
+18
V
±10
mA
VDD + 0.5 V
±10
mA
±10
mA
50
mA
+150
°C
+85
°C
750
mW
500
mW
100
mW
HEF4020B_4
Product data sheet
Rev. 04 — 4 December 2008
© NXP B.V. 2008. All rights reserved.
4 of 13
Share Link: 