AK4396_ 查看數據表（PDF） - Asahi Kasei Microdevices

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AK4396_

AKD4396-SBW Evaluation board

Asahi Kasei Microdevices 

ASAHI KASEI

[AKD4396-SBW]

The frequency of the master clock output is set by OCKS0 and OCKS1 as shown in Table 4.

OCKS1

0

1

1

OCKS0

0

0

1

MCLK Frequency

256fs @fs=88.2/96kHz

512fs @32/44.1/48kHz

128fs @176.4/192kHz

Table 4 MCLK Clock

Default

„ SW1 setting

[SW1](PDN): Reset of AK4396. Select “H” during operation.

 External Analog Circuit

The differential output circuit and LPF is implemented on board. The differential outputs of AK4396 is buffered by non-inverted circuit(2nd

order LPF, fc=182k, Q=0.637, G=+3.9dB). LPF adds differential outputs(1st order LPF, fc=284k, G=-0.84dB). NJM5534D is used for

op-amp on this board that has low noise and high voltage torelance characteristics. Analog signal is output via BNC connectors on the board.

The output level is about 2.8Vrms (typ@VREF=5.0V) by BNC.

100u

AOUTL- +

330

3.3n

180

3.9n

37

2

+

-4

6

NJM5534D

680

+ 10u

0.1u

10u

+

0.1u

100u

AOUTL+ +

330

3.3n

180

3.9n

3

7

+

2-

6

4

NJM5534D

680

+ 10u

0.1u

10u

+

0.1u

+15

-15

620

620

560

0.1u +10u

1.0n

2 - 4 6 100

3 +7

Lch

1.0n NJM5534D

0.1u

+ 10u

Figure 4 External Analog Filter

AKD4396-SBW 40kHz (Double) 80kHz (quad)

Filter

Internal Filter

-0.3dB

-1dB

External LPF

-0.19dB

-0.85dB

Total

-0.49dB

-1.85dB

This table shows typical value.

Table 5 Frequency Responses

<KM078102>

4

2005/06

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