33975A_05 查看數據表（PDF） - Freescale Semiconductor

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33975A_05

Multiple Switch Detection Interface with Suppressed Wake-Up and 32mA Wetting Current

Freescale Semiconductor 

STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics (continued)

Characteristics noted under conditions of 3.0 V ≤ VDD ≤ 5.5 V, 8.0 V ≤ VPWR ≤ 28V, -40°C ≤ TC ≤ 125°C unless otherwise

noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.

Characteristic

Symbol

Min

Typ

Max

Unit

DIGITAL INTERFACE

Input Logic High-Voltage Thresholds (10)

Input Logic Low-Voltage Thresholds (10)

SCLK, SI, Tri-State SO Input Current

0.0 V to VDD

CS Input Current

CS = VDD

CS Pull-Up Current

CS = 0.0 V

SO High-State Output Voltage

ISO(high) = -200 µA

SO Low-State Output Voltage

ISO(high) = 1.6 mA

Input Capacitance on SCLK, SI, Tri-State SO (11)

INT Internal Pull-Up Current

INT Voltage

INT = Open Circuit

INT Voltage

IINT = 1.0 mA

WAKE Internal Pull-Up Current

WAKE Voltage

WAKE = Open Circuit

WAKE Voltage

IWAKE = 1.0 mA

WAKE Voltage (11)

Maximum Voltage Applied to WAKE Through External Pull-Up

VIH

0.7 x VDD

–

VDD + 0.3

V

VIL

GND - 0.3

–

0.2 x VDD

V

ISCLK, ISI,

µA

ISO(Tri)

-10

–

10

ICS

µA

-10

–

10

ICS

30

–

VSO(high)

VDD - 0.8

–

VSO(low)

–

–

µA

100

V

VDD

V

0.4

CIN

–

–

–

15

40

V INT (high)

VDD - 0.5

–

V INT (low)

–

0.2

20

pF

100

µA

V

VDD

V

0.4

I WAKE (pu)

20

40

100

µA

V WAKE (high)

V

4.0

4.3

5.3

V WAKE(low)

–

V

0.2

0.4

V WAKE(max)

–

V

–

40

Notes

10. Upper and lower logic threshold voltage levels apply to SI, CS, and SCLK.

11. This parameter is guaranteed by design however, is not production tested.

33975

8

Analog Integrated Circuit Device Data

Freescale Semiconductor

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