AD7274BRMZ-REEL2 查看數據表（PDF） - Analog Devices
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AD7274BRMZ-REEL2 Datasheet PDF : 29 Pages
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AD7273/AD7274
TIMING SPECIFICATIONS
VDD = 2.35 V to 3.6 V; VREF = 2.35 to VDD; TA = TMIN to TMAX, unless otherwise noted.1 Guaranteed by characterization. All input signals
are specified with tr = tf = 2 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
Table 4.
Parameter
fSCLK 2
tCONVERT
tQUIET
t1
t2
t3 4
t44
t5
t6
t74
t8
t9
tPOWER-UP 5
Limit at TMIN, TMAX
AD7273/AD7274
500
48
14 × tSCLK
12 × tSCLK
4
3
6
4
15
0.4 tSCLK
0.4 tSCLK
5
14
5
4.2
1
Unit
kHz min3
MHz max
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns max
μs max
Description
AD7274
AD7273
Minimum quiet time required between bus relinquish and start of
next conversion
Minimum CS pulse width
CS to SCLK setup time
Delay from CS until SDATA three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
SCLK falling edge to SDATA three-state
SCLK falling edge to SDATA three-state
CS rising edge to SDATA three-state
Power-up time from full power-down
1 Sample tested during initial release to ensure compliance. All timing specifications given are with a 10 pF load capacitance. With a load capacitance greater than this
value, a digital buffer or latch must be used.
2 Mark/space ratio for the SCLK input is 40/60 to 60/40.
3 Minimum fSCLK at which specifications are guaranteed.
4 The time required for the output to cross the VIH or VIL voltage.
5 See the Power-Up Times section
t4
SCLK
VIH
SDATA
VIL
Figure 2. Access Time After SCLK Falling Edge
t7
SCLK
VIH
SDATA
VIL
Figure 3. Hold Time After SCLK Falling Edge
t8
SCLK
SDATA
1.4V
Figure 4. SCLK Falling Edge SDATA Three-State
Rev. 0 | Page 7 of 28
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