AD7274BRMZ-REEL2 查看數據表（PDF） - Analog Devices
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AD7274BRMZ-REEL2 Datasheet PDF : 29 Pages
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AD7273/AD7274
TIMING EXAMPLES
For the AD7274, if CS is brought high during the 14th SCLK
rising edge after the two leading zeros and 12 bits of the
conversion are provided, the part can achieve the fastest
throughput rate, 3 MSPS. If CS is brought high during the 16th
SCLK rising edge after the two leading zeros, 12 bits of the
conversion, and two trailing zeros are provided, a throughput
rate of 2.97 MSPS is achievable. This is illustrated in the
following two timing examples.
Timing Example 2
The example in Figure 7 uses a 16 SCLK cycle, fSCLK = 48 MHz,
and the throughput is 2.97 MSPS. This produces a cycle time
of t2 + 12.5(1/fSCLK) + tACQ = 336 ns, where t2 = 6 ns min and
tACQ = 70 ns. Figure 7 shows that tACQ comprises 2.5(1/fSCLK) +
t8 + tQUIET, where t8 = 14 ns max. This satisfies the minimum
requirement of 4 ns for tQUIET.
Timing Example 1
In Figure 6, using a 14 SCLK cycle, fSCLK = 48 MHz, and
the throughput is 3 MSPS. This produces a cycle time of
t2 + 12.5(1/fSCLK) + tACQ = 333 ns, where t2 = 6 ns min and
tACQ = 67 ns. This satisfies the requirement of 60 ns for tACQ.
Figure 6 also shows that tACQ comprises 0.5(1/fSCLK) + t9 + tQUIET,
where t9 = 4.2 ns max. This allows a value of 52.8 ns for tQUIET,
satisfying the minimum requirement of 4 ns.
t1
CS
SCLK
t2
1
tCONVERT
t6
2
3
4
5
t3
SDATA
Z ZERO DB11
THREE-
STATE TWO LEADING
ZEROS
DB10
t4
DB9
B
13
t7
DB1
DB0
1/THROUGHPUT
14
15
16
t5
t8
ZERO ZERO
TWO TRAILING
ZEROS
tQUIET
THREE-STATE
Figure 5. AD7274 Serial Interface Timing 16 SCLK Cycle
t1
CS
SCLK
t2
1
tCONVERT
t6
2
3
4
t3
SDATA
Z ZERO DB11
THREE-
STATE TWO LEADING
ZEROS
DB10
t4
DB9
B
5
13
t5
t7
DB1 DB0
1/THROUGHPUT
14
t9
tQUIET
THREE-STATE
Figure 6.AD7274 Serial Interface Timing 14 SCLK Cycle
CS
SCLK
t1
tCONVERT
t2
B
1
2
3
4
5
12
13
14
15
16
t8
tQUIET
12.5(1/fSCLK)
1/THROUGHPUT
tACQUISITION
Figure 7. Serial Interface Timing 16 SCLK Cycle
Rev. 0 | Page 8 of 28
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