AD7273BRM 查看數據表（PDF） - Analog Devices
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AD7273BRM Datasheet PDF : 20 Pages
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PRELIMINARY TECHNICAL DATA
AD7273/AD7274
Preliminary Technical Data
TIMING SPECIFICATIONS1
(VDD= +2.35 V to +3.6 V; VREF = 2.5V, TA= TMIN to TMAX, unless otherwise noted.)
Parameter
Limit at TMIN, TMAX
AD7273/AD7274
Units
Description
fSCLK 2
tCONVERT
20
52
14 x tSCLK
12 x tSCLK
KHz min3
MHz max
AD7274
AD7273
tQUIET
t1
t2
t
4
3
t
4
4
t5
t6
t
4
7
t
5
8
t
po
we
6
r-up
TBD
10
TBD
TBD
TBD
0.4tSCLK
0.4tSCLK
TBD
TBD
TBD
TBD
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
µs max
Minimum Quiet Time required between Bus Relinquish
and start of Next Conversion
Minimum CS Pulse Width
CS to SCLK Setup Time
Delay from CS Until SDATA Three-State Disabled
Data Access Time After SCLK Falling Edge
SCLK Low Pulse Width
SCLK High Pulse Width
SCLK to Data Valid Hold Time
SCLK Falling Edge to SDATA Three-State
SCLK Falling Edge to SDATA Three-State
Power Up Time from Full Power-down
NOTES
1Guaranteed by Characterization. All input signals are specified with tr=tf=5ns (10% to 90% of VDD) and timed from a voltage level of 1.6Volts.
2Mark/Space ratio for the SCLK input is 40/60 to 60/40.
3Minimum fsclk at which specifications are guaranteed.
4Measured with the load circuit of Figure 1 and defined as the time required for the output to cross the Vih or Vil voltage.
5t8 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number
is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the
timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.
6See Power-up Time section.
Specifications subject to change without notice.
200µA
IOL
TO
OUTPUT
PIN
CL
25pF
200µA
IOH
+1.6V
Figure 1. Load Circuit for Digital Output
Timing Specifications
t4
SCLK
t7
SCLK
SDATA
VIH
VIL
Figure 3. Hold time after SCLK falling edge
t8
SCLK
SDATA
VIH
V
IL
Figure 2. Access time after SCLK falling edge
SDATA
1.6 V
Figure 4. SCLK falling edge to SDATA Three-State
–6–
REV. PrB
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