AD7273 查看數據表（PDF） - Analog Devices
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AD7273 Datasheet PDF : 20 Pages
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PRELIMINARY TECHNICAL DATA
Preliminary Technical Data
AD7273/AD7274
Figures 5 and 6 show some of the timing parameters from the Timing Specifications table.
t1
&6
tconvert
t2
t6
B
SCLK
1
2
3
4
5
t3
t7
t4
13
14
15
16
t5
t8
tquiet
SDATA THREE-
STATE
Z ZERO
2 LEADING
ZERO’S
DB11
DB10
DB9
DB1
DB0
1/ THROUGHPUT
ZERO
ZE RO
2 TRAILING
ZE RO ’S
THREE-STATE
Figure 5. AD7274 Serial Interface Timing Diagram
Timing Example 1
From Figure 6, having fSCLK = 52 MHz and a throughput of 3MSPS, gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ =
333 ns. With t2 = TBD ns min, this leaves tACQ to be TBD ns. This TBD ns satisfies the requirement of 50 ns for tACQ.
Figure 6 shows that, tACQ comprises of 2.5(1/fSCLK) + t8 + tQUIET, where t8 = TBD ns max. This allows a value of TBD
ns for tQUIET satisfying the minimum requirement of TBD ns.
Timing Example 2
Having fSCLK = 20 MHz and a throughput of 1.5 MSPS, gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 666 ns.
With t2 = TBD ns min, this leaves tACQ to be TBD ns. This TBD ns satisfies the requirement of 50 ns for tACQ. From
Figure 6, tACQ comprises of 2.5(1/fSCLK) + t8 + tQUIET, where t8 = TBD ns max. This allows a values of TBD ns for
tQUIET satisfying the minimum requirement of TBD ns.
&6
SCLK
t1
t2
1
tconvert
B
2
3
4
5
12
13
14
15
16
t8
tqu iet
12.5(1/fSCLK)
1/THROUGHPUT
tacquisition
Figure 6. Serial Interface Timing Example
REV. PrB
–7–
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