GMS97C1051 查看數據表（PDF） - Hynix Semiconductor
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GMS97C1051 Datasheet PDF : 19 Pages
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8-Bit CMOS Microcontorller
Figure 3. Time/Counter 0 Input Clock Logic
GMS97C1051/L1051
fosc
¡ À12
P3.4/T0
max fosc/24
TR 0
TCON
Gate
=1
TMOD
P3.2/INT0
P3.3/INT1
C/T
TMOD
0
1
&
¡ Ã1
fosc/12
Control
Timer 0
Input Clock
Interrupt System
The GMS97C1051/L1051 provides 3 interrupt
sources ( two external interrupts and timer inter-
rupt ) with two priority levels. Figure 4 gives a
general overview of the interrupt sources and illus-
trates the request and control flags.
A low-priority interrupt can itself be interrupted by
a high-priority interrupt, but not by another low
priority interrupt. A high-priority interrupt can-
not be interrupted by any other interrupt source.
If two requests of different priority levels are re-
ceived simultaneously, the request of higher
priority is serviced. If requests of the same prior-
ity level are received simultaneously, an internal
polling sequence determines which request is ser-
viced. Thus within each priority level there is a
second priority structure determined by the polling
sequence like Table 6.
Figure 4. Interrupt Request Sources
¢¹
P3.2/
INT0
IT0
TCON.0
IE0
TCON.1
EX0
IE.0
High Priority
Low Priority
PX0
IP.0
Timer 0 Overflow
P3.3/
INT1
IT1
TCON.2
TF0
TCON.5
ET0
IE.1
¢¹
IE1
TCON.3
EX1
IE.2
PT0
IP.1
PX1
IP.2
EA
IE.7
27
Hynix semiconductor
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