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73S8010R-IM/F 查看數據表(PDF) - Teridian Semiconductor Corporation

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产品描述 (功能)
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73S8010R-IM/F
TERIDIAN
Teridian Semiconductor Corporation TERIDIAN
73S8010R-IM/F Datasheet PDF : 24 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
MICROCONTROLLER INTERFACE
73S8010R
Low Cost Smart Card Interface
DATA SHEET
NAME
INT
SAD0
SAD1
SAD2
SCL
SDA
I/OUC
AUX1UC
AUX2UC
PIN
(SO)
23
1
2
3
PIN
(QFN)
22
29
30
31
DESCRIPTION
Interrupt output(negative assertion). Interrupt output signal to the processor. A 20kpull up to
VDD is provided internally
Serial device address bits. Digital inputs for address selection that allows for the connection of up
to 8 devices in parallel. Address selections as follows:
SAD2
0
0
0
0
1
1
1
1
SAD1
0
0
1
1
0
0
1
1
SAD0
0
1
0
1
0
1
0
1
I2C Address (7 bits)
40h
42h
44h
46h
48h
4Ah
4Ch
4Eh
19 18
20 19
26 26
27 27
28 28
Note: Pins SADO and SAD1 are internally pulled-down and SAD2 is internally pulled-up.
The default address when left unconnected is 48h.
I2C clock signal input
I2C bi-directional serial data signal
System controller data I/O to/from the card. Includes internal pull-up resistor to VDD
System controller auxiliary data I/O to/from the card. Includes internal pull-up resistor to VDD
System controller auxiliary data I/O to/from the card. Includes internal pull-up resistor to VDD
Page: 4 of 24
© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5

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