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74LS76A

Dual JK Flip-Flop with Set and Clear

ON Semiconductor 

SN74LS76A

Dual JK Flip-Flop

with Set and Clear

The SN74LS76A offers individual J, K, Clock Pulse, Direct Set and

Direct Clear inputs. These dual flip-flops are designed so that when

the clock goes HIGH, the inputs are enabled and data will be accepted.

The Logic Level of the J and K inputs will perform according to the

Truth Table as long as minimum set-up times are observed. Input data

is transferred to the outputs on the HIGH-to-LOW clock transitions.

MODE SELECT – TRUTH TABLE

OPERATING

INPUTS

OUTPUTS

MODE

SD

CD

J

K

Q

Q

Set

L

H

X

X

H

L

Reset (Clear)

H

L

X

X

L

H

*Undetermined

L

L

X

X

H

H

Toggle

H

H

h

h

q

q

Load “0” (Reset)

H

H

l

h

L

H

Load “1” (Set)

H

H

h

l

H

L

Hold

H

H

l

l

q

q

* Both outputs will be HIGH while both SD and CD are LOW, but the output

states are unpredictable if SD and CD go HIGH simultaneously.

H, h = HIGH Voltage Level

L, I = LOW Voltage Level

X = Immaterial

l, h (q) = Lower case letters indicate the state of the referenced input

i, h (q) = (or output) one setup time prior to the HIGH–to–LOW clock transition

http://onsemi.com

LOW

POWER

SCHOTTKY

16

1

PLASTIC

N SUFFIX

CASE 648

16

1

SOIC

D SUFFIX

CASE 751B

GUARANTEED OPERATING RANGES

Symbol

Parameter

Min Typ Max Unit

VCC

TA

Supply Voltage

Operating Ambient

Temperature Range

4.75 5.0 5.25

V

0

25

70

°C

IOH

Output Current – High

IOL

Output Current – Low

–0.4 mA

8.0

mA

ORDERING INFORMATION

Device

Package

Shipping

SN74LS76AN

16 Pin DIP 2000 Units/Box

SN74LS76AD

SOIC–16 38 Units/Rail

SN74LS76ADR2 SOIC–16 2500/Tape & Reel

© Semiconductor Components Industries, LLC, 2001

1

October, 2001 – Rev. 7

Publication Order Number:

SN74LS76A/D

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