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9014

Fairchild QFET for Synchronous Rectification DC to DC Converters

Fairchild Semiconductor 

2) C1/C2 design

(1) Output Capacitor, C2

C2 can be calculated from equation (4-2), which is derived from equations (3-13) (output volt-

age ripple calculation equation) and (3-14).

C2 ≥ 8-----f--s--∆-∆---i-v-L---o---u---t

≥ -8-----×-----3---1----0----[---k--2-H----[--zA---]--]--×----0----.--0----4----[--V-----] ≥ 20.16[µF]

C2 = 1500[µF] × 10………………(4 – 2)

A capacitor with low ESR should be used, if possible, to minimize the ESR loss. The maximum

ESR of C2 can be calculated from equation (4-3) below.

ESR ≤ ∆----∆V----i-o-L--u----t

≤ 0----.-2-0---[-4--A--[--V-]----]- = 0.02[Ω]…………(4 – 3)

C2 is set with a value much greater than the minimum value, and connected in parallel to

reduce the output voltage ripple and ESR.

(2) Input Capacitor, C1

In order to reduce ESR, C1, which is used as the input low pass filter, should be designed in

parallel, if possible. The following equation (4-4) shows the calculation for C1.

C1 ≥ -I--i-∆-n---vT---i--on---n-

≥ -8---.--4----7----[--A------]--0-×--.--5-1---[-.-5-V---8--]--[---µ----s---e----c-------] ≥ 26.77[µF]

C1 = 1200[µF] × 5…………(4 – 4)

4-2. Power Loss Analysis

The losses generated mainly in the synchronous rectification DC-DC converter in Figure 4-1

are as follows:

• MOSFET conduction losses: I2RDS(on)

• Inductor equivalent resistance DC losses

• PCB copper losses

• MOSFET gate-charge losses

• Diode-conduction losses

• Transition losses of power MOSFET

• Capacitor ESR losses

• Losses due to the PWM control IC

Among the losses, conduction losses (I2RDS(on)), gate-charge losses, and transition losses

are specifically associated with the MOSFET and can be represented by the following equa-

tion.

11

Rev. B, July 2000

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