9014 查看數據表（PDF） - Fairchild Semiconductor
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9014 Datasheet PDF : 16 Pages
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∆Q, the portion indicated by the thick line in Figure 3-6, can be calculated as a triangular area
of ∆iL/2 in height and Ts/2 in width.
∆Q
=
12---
-∆--2-i---L-
T--2----s
…
……
(
3
–
13
)
The following equation is derived when equation (3-12) is substituted into equation (3-13),
where the peak-to-peak output voltage ripple component is ∆vout:
∆vout = ∆---C--Q-- = -D----(---1-----–--8---D-L---)--C-V-----i-n---T-----s2--= -π---2---(---1-----–---2--D-----)--V-----o---u---tff---cs- 2………(3 – 14)
where:
fc
=
---------1---------- : output
2π LC
LPF resonant
frequency
fs: switching frequency
As shown by equation (3-14), the output voltage ripple can be reduced, if fs is increased or if it
is designed so that fc becomes fc<<fs.
4. Synchronous Rectification DC-DC Converter Design
4-1. Design Example
The design in Figure 4-1 outputs the processor core voltage VccCORE (1.3[V] ~ 3.5[V]), Vtt ter-
mination (1.5[V]), Vclock (2.5[V]), and Vagp (Selectable 1.5[V] / 3.3[V]) using the Fairchild PWM
control IC RC5058. Of these outputs, only VccCORE is output by the synchronous rectification
DC-DC converter and the remaining outputs are output through the linear regulator. This sec-
tion describes the calculations for the input (L1) / output (L2) inductor and input (C1) / output
(C2) capacitor for the synchronous rectification DC-DC converter design shown in Figure 4-1.
The following initial design conditions are set.
•
D
=
0.49
=
V-----i--n----+---V--V--o---D-u---t-–--+--V---V--D--D--S---(--o---n----)--)
• fs = 310[kHz]
• VDS(on) = 0.37[V] (Q1’s on-state drain-to-source voltage = Iout × RDS(on))
• ∆iL < 2[A]: set it to twice the value of the minimum output current to operate in the
continuous mode.
• Vout = 2.0[V]: refer to table 3-1.
• Output voltage ripple ∆vout < 0.04[V]: set within ±1[%] of Vout = 2.0[V]
• Input voltage ripple ∆vin < 0.5[V]: set within ±5[%] of Vin = 5[V]
• Input current Iin = 8.47[A]: set to 85% efficiency at max load condition
(Vin = 5[V], Vout = 2.0[V], Iout = 18[A]).
9
Rev. B, July 2000
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