KSZ9031RNX 查看數據表（PDF） - Micrel

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产品描述 (功能)

生产厂家

KSZ9031RNX

Gigabit Ethernet Transceiver with RGMII Support

Micrel 

Micrel, Inc.

KSZ9031RNX

List of Figures

Figure 1. KSZ9031RNX Block Diagram ............................................................................................................................... 15

Figure 2. KSZ9031RNX 1000Base-T Transceiver Block Diagram – Single Channel.......................................................... 17

Figure 3. Auto-Negotiation Flow Chart................................................................................................................................. 20

Figure 4. KSZ9031RNX RGMII Interface............................................................................................................................. 23

Figure 5. Local (Digital) Loopback ....................................................................................................................................... 30

Figure 6. Remote (Analog) Loopback .................................................................................................................................. 31

Figure 7. LPI Mode (Refresh Transmissions and Quiet Periods) ........................................................................................ 34

Figure 8. LPI Transition – RGMII (1000Mbps) Transmit ...................................................................................................... 35

Figure 9. LPI Transition – RGMII (100Mbps) Transmit ........................................................................................................ 36

Figure 10. LPI Transition – RGMII (1000Mbps) Receive ..................................................................................................... 36

Figure 11. LPI Transition – RGMII (100Mbps) Receive ....................................................................................................... 37

Figure 12. RGMII v2.0 Spec (Figure 2 – Multiplexing and Timing Diagram – Original RGMII (v1.3) with external delay) ... 69

Figure 13. RGMII v2.0 Spec (Figure 3 – Multiplexing and Timing Diagram – RGMII-ID (v2.0) with internal chip delay) ..... 70

Figure 14. Auto-Negotiation Fast Link Pulse (FLP) Timing .................................................................................................. 72

Figure 15. MDC/MDIO Timing............................................................................................................................................... 73

Figure 16. Power-Up/Power-Down/Reset Timing ................................................................................................................. 74

Figure 17. Reset Circuit for Triggering by Power Supply...................................................................................................... 75

Figure 18. Reset Circuit for Interfacing with CPU/FPGA Reset Output ................................................................................ 75

Figure 19. Rest Circuit with MIC826 Voltage Supervisor...................................................................................................... 76

Figure 20. Reference Circuits for LED Strapping Pins ......................................................................................................... 76

Figure 21. 25MHz Crystal/Oscillator Reference Clock Connection ...................................................................................... 77

Figure 22. Typical Gigabit Magnetic Interface Circuit ........................................................................................................... 78

May 14, 2015

6

Revision 2.2

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