KSZ9031RNX 查看數據表（PDF） - Microchip Technology
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KSZ9031RNX Datasheet PDF : 78 Pages
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KSZ9031RNX
After auto-negotiation is completed, the link status is updated in Register 1h, Bit [2], and the link partner capabilities are
updated in Registers 5h, 6h, 8h, and Ah.
The auto-negotiation finite state machines use interval timers to manage the auto-negotiation process. The duration of
these timers under normal operating conditions is summarized in Table 3-2.
TABLE 3-2: AUTO-NEGOTIATION TIMERS
Auto-Negotiation Interval Timers
Transmit Burst Interval
Transmit Pulse Interval
FLP Detect Minimum Time
FLP Detect Maximum Time
Receive Minimum Burst Interval
Receive Maximum Burst Interval
Data Detect Minimum Interval
Data Detect Maximum Interval
NLP Test Minimum Interval
NLP Test Maximum Interval
Link Loss Time
Break Link Time
Parallel Detection Wait Time
Link Enable Wait Time
Time Duration
16 ms
68 µs
17.2 µs
185 µs
6.8 ms
112 ms
35.4 µs
95 µs
4.5 ms
30 ms
52 ms
1480 ms
830 ms
1000 ms
3.8 10/100 Mbps Speeds Only
Some applications require link-up to be limited to 10/100 Mbps speeds only.
After power-up/reset, the KSZ9031RNX can be restricted to auto-negotiate and link-up to 10/100 Mbps speeds only by
programming the following register settings:
1. Set Register 0h, Bit [6] = ‘0’ to remove 1000 Mbps speed.
2. Set Register 9h, Bits [9:8] = ‘00’ to remove Auto-Negotiation advertisements for 1000 Mbps full-/half-duplex.
3. Write a ‘1’ to Register 0h, Bit [9], a self-clearing bit, to force a restart of Auto-Negotiation.
Auto-Negotiation and 10BASE-T/100BASE-TX speeds use only differential pairs A (pins 2, 3) and B (pins 5, 6). Differ-
ential pairs C (pins 7, 8) and D (pins 10, 11) can be left as no connects.
3.9 RGMII Interface
The Reduced Gigabit Media Independent Interface (RGMII) supports on-chip data-to-clock delay timing according to
the RGMII Version 2.0 Specification, with programming options for external delay timing and to adjust and correct TX
and RX timing paths.
RGMII provides a common interface between RGMII PHYs and MACs, and has the following key characteristics:
• Pin count is reduced from 24 pins for the IEEE Gigabit Media Independent Interface (GMII) to 12 pins for RGMII.
• All speeds (10 Mbps, 100 Mbps, and 1000 Mbps) are supported at both half- and full-duplex.
• Data transmission and reception are independent and belong to separate signal groups.
• Transmit data and receive data are each four bits wide, a nibble.
In RGMII operation, the RGMII pins function as follows:
• The MAC sources the transmit reference clock, TXC, at 125 MHz for 1000 Mbps, 25 MHz for 100 Mbps, and
2.5 MHz for 10 Mbps.
• The PHY recovers and sources the receive reference clock, RXC, at 125 MHz for 1000 Mbps, 25 MHz for
100 Mbps, and 2.5 MHz for 10 Mbps.
• For 1000BASE-T, the transmit data, TXD[3:0], is presented on both edges of TXC, and the received data,
RXD[3:0], is clocked out on both edges of the recovered 125 MHz clock, RXC.
• For 10BASE-T/100BASE-TX, the MAC holds TX_CTL low until both PHY and MAC operate at the same speed.
DS00002117C-page 18
2016 Microchip Technology Inc.
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