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KSZ9031RNX

Gigabit Ethernet Transceiver with RGMII Support

Microchip Technology 

KSZ9031RNX

3.9.3 RGMII PAD SKEW REGISTERS

Pad skew registers are available for all RGMII pins (clocks, control signals, and data bits) to provide programming

options to adjust or correct the timing relationship for each RGMII pin. Because RGMII is a source-synchronous bus

interface, the timing relationship needs to be maintained only within the RGMII pin’s respective timing group.

• RGMII transmit timing group pins: GTX_CLK, TX_EN, TXD[3:0]

• RGMII receive timing group pins: RX_CLK, RX_DV, RXD[3:0]

Table 3-4 details the four registers located at MMD Address 2h that are provided for pad skew programming.

TABLE 3-4: RGMII PAD SKEW REGISTERS

Address

Name Description

Mode

Default

MMD Address 2h, Register 4h – RGMII Control Signal Pad Skew

2.4.15:8 Reserved Reserved

RW

2.4.7:4

RX_DV RGMII RX_CTL output pad skew control (0.06 ns/

RW

Pad Skew step)

2.4.3:0

TX_EN RGMII TX_CTL input pad skew control (0.06 ns/

RW

Pad Skew step)

MMD Address 2h, Register 5h – RGMII RX Data Pad Skew

0000_0000

0111

0111

2.5.15:12

RXD3 RGMII RXD3 output pad skew control (0.06 ns/

RW

Pad Skew step)

2.5.11:8

RXD2 RGMII RXD2 output pad skew control (0.06 ns/

RW

Pad Skew step)

2.5.7:4

RXD1 RGMII RXD1 output pad skew control (0.06 ns/

RW

Pad Skew step)

2.5.3:0

RXD0 RGMII RXD0 output pad skew control (0.06 ns/

RW

Pad Skew step)

MMD Address 2h, Register 6h – RGMII TX Data Pad Skew

0111

0111

0111

0111

2.6.15:12

TXD3

RGMII TXD3 input pad skew control (0.06 ns/step)

RW

Pad Skew

2.6.11:8

TXD2

RGMII TXD2 input pad skew control (0.06 ns/step)

RW

Pad Skew

2.6.7:4

TXD1

RGMII TXD1 input pad skew control (0.06 ns/step)

RW

Pad Skew

2.6.3:0

TXD0

RGMII TXD0 input pad skew control (0.06 ns/step)

RW

Pad Skew

0111

0111

0111

0111

MMD Address 2h, Register 8h – RGMII Clock Pad Skew

2.8.15:10 Reserved Reserved

RW

0000_00

2.8.9:5

GTX_CLK RGMII GTX_CLK input pad skew control (0.06 ns/

RW

Pad Skew step)

01_111

2.8.4:0

RX_CLK RGMII RX_CLK output pad skew control (0.06 ns/

RW

0_1111

Pad Skew step)

The RGMII control signals and data bits have 4-bit skew settings, while the RGMII clocks have 5-bit skew settings.

Each register bit is approximately a 0.06 ns step change. A single-bit decrement decreases the delay by approximately

0.06 ns, while a single-bit increment increases the delay by approximately 0.06 ns.

Table 3-5 and Table 3-6 list the approximate absolute delay for each pad skew (value) setting.

DS00002117C-page 20

 2016 Microchip Technology Inc.

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