8737-11 查看數據表（PDF） - Integrated Device Technology
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8737-11 Datasheet PDF : 17 Pages
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8737-11 DATA SHEET
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 5A to 5E show interface
examples for the PCLK/nPCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. If the driver is from another vendor, use their
termination recommendation. Please consult with the vendor
of the driver component to confirm the driver
termination requirements.
3.3V
CML
Zo = 50 Ohm
Zo = 50 Ohm
3.3V
R1
R2
50
50
3.3V
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
2.5V
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
2.5V
R3
R4
120
120
3.3V
PCLK
R1
R2
120
120
nPCLK
HiPerClockS
PCLK/nPCLK
FIGURE 5A. PCLK/nPCLK INPUT DRIVEN
BY A CML DRIVER
FIGURE 5B. PCLK/nPCLK INPUT DRIVEN
BY AN SSTL DRIVER
3.3V
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
3.3V
R3
R4
125
125
3.3V
PCLK
nPCLK HiPerClockS
Input
R1
R2
84
84
3.3V
LVDS
Zo = 50 Ohm
R5
100
Zo = 50 Ohm
3.3V
3.3V
R3
R4
1K
1K
C1
PCLK
C2
nPCLK
HiPerClockS
PCLK/nPCLK
R1
R2
1K
1K
FIGURE 5C. PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 5D. PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
3.3V
3.3V LVPECL
3.3V
Zo = 50 Ohm
R3
R4
84
84
C1
Zo = 50 Ohm
C2
R5
100 - 200
R6
100 - 200
R1
R2
125 125
3.3V
PCLK
nPCLK HiPerClockS
PCLK/nPCLK
FIGURE 5E. PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
LOW SKEW, ÷1/÷2
10
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
REVISION C 2/13/15
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