8737-11 查看數據表（PDF） - Integrated Device Technology

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8737-11

Low Skew, ÷1/÷2 Differential-to-3.3V LVPECL Clock Generator

Integrated Device Technology 

8737-11 DATA SHEET

TABLE 3A. CONTROL INPUT FUNCTION TABLE

Inputs

Outputs

MR CLK_EN CLK_SEL Selected Source QA0, QA1

nQA0, nQA1

QB0, QB1

nQB0, nQB1

1

X

X

X

LOW

HIGH

LOW

HIGH

0

0

0

CLK, nCLK Disabled; LOW Disabled; HIGH Disabled; LOW Disabled; HIGH

0

0

1

PCLK, nPCLK Disabled; LOW Disabled; HIGH Disabled; LOW Disabled; HIGH

0

1

0

CLK, nCLK

Enabled

Enabled

Enabled

Enabled

0

1

1

PCLK, nPCLK

Enabled

Enabled

Enabled

Enabled

After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge

as shown if Figure 1.

In the active mode, the state of the outputs are a function of the CLK , nCLK and PCLK, nPCLK inputs as described

in Table 3B.

nCLK, nPCLK

CLK, PCLK

CLK_EN

nQA0, nQA1,

nQB0, nQB1

QA0, QA1,

QB0, QB1

FIGURE 1. CLK_EN TIMING DIAGRAM

TABLE 3B. CLOCK INPUT FUNCTION TABLE

Inputs

CLK or PCLK nCLK or nPCLK

Outputs

QAx nQAx QBx nQBx

Input to Output Mode

Polarity

0

0

LOW HIGH LOW HIGH Differential to Differential Non Inverting

1

1

HIGH LOW HIGH LOW

Differential to Differential

Non Inverting

0

Biased; NOTE 1 LOW HIGH LOW HIGH Single Ended to Differential Non Inverting

1

Biased; NOTE 1 HIGH LOW HIGH LOW Single Ended to Differential Non Inverting

Biased; NOTE 1

0

HIGH LOW HIGH LOW Single Ended to Differential

Inverting

Biased; NOTE 1

1

LOW HIGH LOW HIGH Single Ended to Differential

Inverting

NOTE 1: Please refer to the Application Information section, “Wiring the Differential Input to Accept Single Ended Levels”.

REVISION C 2/13/15

3

LOW SKEW, ÷1/÷2

DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR

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