8737-11 查看數據表（PDF） - Integrated Device Technology
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8737-11 Datasheet PDF : 17 Pages
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8737-11 DATA SHEET
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions Minimum Typical
I
Input High Current
IH
VIN = VCC = 3.465V
VIN = VCC = 3.465V
IIL
Input Low Current
VIN = 0V, VCC = 3.465V
VIN = 0V, VCC = 3.465V
-5
-150
VPP
Peak-to-Peak Input Voltage
0.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
VEE + 1.5
VOH
Output High Voltage; NOTE 3
VCC - 1.4
VOL
Output Low Voltage; NOTE 3
VCC - 2.0
VSWING Peak-to-Peak Output Voltage Swing
0.65
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
NOTE 3: Outputs terminated with 50Ω to VCC - 2V.
Maximum
150
5
1
VCC
VCC - 0.9
VCC - 1.7
1.0
Units
µA
µA
µA
µA
V
V
V
V
V
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions Minimum Typical Maximum Units
fMAX
Output Frequency
CLK, nCLK
1.3
tPD
Propagation Delay; NOTE 1
PCLK, nPCLK
ƒ ≤ 650MHz
1.2
650
MHz
1.7
ns
1.6
ns
tsk(o) Output Skew; NOTE 2, 4
60
ps
tsk(b) Bank Skew; NOTE 4
Bank A
Bank B
20
ps
35
ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4
200
ps
tjit
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section, NOTE 5
0.04
ps
tR
Output Rise Time
tF
Output Fall Time
odc
Output Duty Cycle
20% to 80% @ 50MHz 300
700
ps
20% to 80% @ 50MHz 300
700
ps
48
50
52
%
All parameters measured at 500MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Driving only one input clock.
REVISION C 2/13/15
5
LOW SKEW, ÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
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