85304-01 查看數據表（PDF） - Integrated Device Technology
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85304-01 Datasheet PDF : 15 Pages
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85304-01 Data Sheet
Function Tables
Table 3A. Control Input Function Table
Inputs
CLK_EN
CLK_SEL
0
0
0
1
1
0
1
1
Selected Source
CLK0, nCLK0
CLK1, nCLK1
CLK0, nCLK0
CLK1, nCLK1
Outputs
Q0:Q4
nQ0:nQ4
Disabled; LOW
Disabled; HIGH
Disabled; LOW
Disabled; HIGH
Enabled
Enabled
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLKx, nCLKx inputs as described in Table 3B.
nCLK[0:1]
CLK[0:1]
CLK_EN
Disabled
Enabled
nQ[0:4]
Q[0:4]
Figure 1. CLK_EN Timing Diagram
Table 3B. Clock Input Function Table
Inputs
CLK0 or CLK1
nCLK0 or nCLK1
0
1
1
0
0
Biased; NOTE 1
1
Biased; NOTE 1
Biased; NOTE 1
0
Biased; NOTE 1
1
Outputs
Q[0:4]
nQ[0:4]
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single-Ended to
Differential
Single-Ended to
Differential
Single-Ended to
Differential
Single-Ended to
Differential
Polarity
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
Inverting
NOTE 1: Please refer to the Application Information section, Wiring the Differential Input to Accept Single-Ended Levels.
©2015 Integrated Device Technology, Inc
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Revision E December 2, 2015
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