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85304-01

Low Skew, 1-to-5, Differential-to-3.3V LVPECL Fanout Buffer

Integrated Device Technology 

85304-01 Data Sheet

Recommendations for Unused Input and Output Pins

Inputs:

LVCMOS Control Pins

All control pins have internal pullup or pulldown; additional resistance

is not required but can be added for additional protection. A 1k

resistor can be used.

CLK/nCLK Inputs

For applications not requiring the use of the differential input, both

CLK and nCLK can be left floating. Though not required, but for

additional protection, a 1k resistor can be tied from CLK to ground.

Outputs:

LVPECL Outputs

All unused LVPECL output pairs can be left floating. We recommend

that there is no trace attached. Both sides of the differential output

pair should either be left floating or terminated.

Termination for 3.3V LVPECL Outputs

The clock layout topology shown below is a typical termination for

LVPECL outputs. The two different layouts mentioned are

recommended only as guidelines.

The differential outputs are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must be

used for functionality. These outputs are designed to drive 50

transmission lines. Matched impedance techniques should be used

to maximize operating frequency and minimize signal distortion.

Figures 3A and 3B show two different layouts which are

recommended only as guidelines. Other suitable clock layouts may

exist and it would be recommended that the board designers

simulate to guarantee compatibility across all printed circuit and clock

component process variations.

3.3V

3.3V

R3

R4

125

125

3.3V

Zo = 50

+

Zo = 50

R1

84

_

R2

84

Input

Figure 3A. 3.3V LVPECL Output Termination

Figure 3B. 3.3V LVPECL Output Termination

©2015 Integrated Device Technology, Inc

9

Revision E December 2, 2015

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