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ICS8531-01

LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER

Integrated Device Technology 

ICS8531-01

LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER

TERMINATION FOR LVPECL OUTPUTS

The clock layout topology shown below is a typical termina-

tion for LVPECL outputs. The two different layouts mentioned

are recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, ter-

minating resistors (DC current path to ground) or current

sources must be used for functionality. These outputs are

designed to drive 50Ω transmission lines. Matched imped-

ance techniques should be used to maximize operating fre-

quency and minimize signal distortion. Figures 5A and 5B

show two different layouts which are recommended only as

guidelines. Other suitable clock layouts may exist and it

would be recommended that the board designers simulate

to guarantee compatibility across all printed circuit and clock

component process variations.

Zo = 50Ω

FOUT

FIN

Zo = 50Ω

50Ω

RTT =

1

((VOH + VOL) / (VCC – 2)) – 2

Zo

50Ω

VCC - 2V

RTT

FOUT

3.3V

125Ω

125Ω

Zo = 50Ω

FIN

Zo = 50Ω

84Ω

84Ω

FIGURE 5A. LVPECL OUTPUT TERMINATION

FIGURE 5B. LVPECL OUTPUT TERMINATION

IDT™ / ICS™ 1-TO-9, 3.3V LVPECL FANOUT BUFFER

11

ICS8531AY-01 REV. F APRIL 11, 2007

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