ICS8531-01 查看數據表（PDF） - Integrated Device Technology

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ICS8531-01

LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER

Integrated Device Technology 

ICS8531-01

LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER

TABLE 3A. CONTROL INPUT FUNCTION TABLE

Inputs

Outputs

CLK_EN

CLK_SEL

Selected Sourced

Q0:Q8

nQ0:nQ8

0

0

CLK, nCLK

Disabled; LOW

Disabled; HIGH

0

1

PCLK, nPCLK

Disabled; LOW

Disabled; HIGH

1

0

CLK, nCLK

Enabled

Enabled

1

1

PCLK, nPCLK

Enabled

Enabled

After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge

as shown in Figure 1.

In the active mode, the state of the outputs are a function of the CLK, nCLK and PCLK, nPCLK inputs as described

in Table 3B.

nCLK, nPCLK

CLK, PCLK

CLK_EN

Disabled

Enabled

nQ0:nQ8

Q0:Q8

FIGURE 1. CLK_EN TIMING DIAGRAM

TABLE 3B. CLOCK INPUT FUNCTION TABLE

Inputs

CLK or PCLK nCLK or nPCLK

Outputs

Q0:Q8

nQ0:nQ8

Input to Output Mode

Polarity

0

1

LOW

HIGH

Differential to Differential

Non Inverting

1

0

HIGH

LOW

Differential to Differential

Non Inverting

0

Biased; NOTE 1

LOW

HIGH

Single Ended to Differential Non Inverting

1

Biased; NOTE 1

HIGH

LOW

Single Ended to Differential Non Inverting

Biased; NOTE 1

0

HIGH

LOW

Single Ended to Differential

Inverting

Biased; NOTE 1

1

LOW

HIGH

Single Ended to Differential

Inverting

NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".

IDT™ / ICS™ 1-TO-9, 3.3V LVPECL FANOUT BUFFER

3

ICS8531AY-01 REV. F APRIL 11, 2007

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