MC100H640 查看數據表（PDF） - Motorola => Freescale
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MC100H640 Datasheet PDF : 8 Pages
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
68030/040
PECL-TTL Clock Driver
MC10H640
MC100H640
The MC10H/100H640 generates the necessary clocks for the 68030,
68040 and similar microprocessors. It is guaranteed to meet the clock
specifications required by the 68030 and 68040 in terms of part–to–part
skew, within–part skew and also duty cycle skew.
The user has a choice of using either TTL or PECL (ECL referenced to
+5.0V) for the input clock. TTL clocks are typically used in present MPU
systems. However, as clock speeds increase to 50MHz and beyond, the
inherent superiority of ECL (particularly differential ECL) as a means of
clock signal distribution becomes increasingly evident. The H640 also
uses differential PECL internally to achieve its superior skew
characteristic.
The H640 includes divide–by–two and divide–by–four stages, both to
achieve the necessary duty cycle skew and to generate MPU clocks as
required. A typical 50MHz processor application would use an input clock
running at 100MHz, thus obtaining output clocks at 50MHz and 25MHz
(see Logic Symbol).
The 10H version is compatible with MECL 10H™ ECL logic levels,
while the 100H version is compatible with 100K levels (referenced
to +5.0V).
• Generates Clocks for 68030/040
• Meets 030/040 Skew Requirements
• TTL or PECL Input Clock
• Extra TTL and PECL Power/Ground Pins
• Asynchronous Reset
• Single +5.0V Supply
68030/040
PECL–TTL CLOCK
DRIVER
FN SUFFIX
PLASTIC PACKAGE
CASE 776–02
Function
Reset (R): LOW on RESET forces all Q outputs LOW and all Q outputs HIGH.
Power–Up: The device is designed to have the POS edges of the ÷2 and ÷4 outputs synchronized at power up.
Select (SEL): LOW selects the ECL input source (DE/DE). HIGH selects the TTL input source (DT).
The H640 also contains circuitry to force a stable state of the ECL input differential pair, should both sides be left open. In this
case, the DE side of the input is pulled LOW, and DE goes HIGH.
VT VT Q1 GT GT Q0 VT
25 24 23 22 21 20 19
Q2 26
18 VBB
GT 27
17 DE
GT 28
Q3 1
VT 2
16 DE
Pinout: 28–Lead PLCC
(Top View)
15 VE
14 R
VT 3
13 GE
Q0 4
12 DT
5 6 7 8 9 10 11
Q1 GT GT Q4 Q5 VT SEL
11/93
© Motorola, Inc. 1996
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