M41T81(2006) 查看數據表（PDF） - STMicroelectronics

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M41T81
(Rev.:2006)

Serial access Real-Time Clock with alarm

STMicroelectronics 

Operation

2

Operation

M41T81

The M41T81 clock operates as a slave device on the serial bus. Access is obtained by

implementing a start condition followed by the correct slave address (D0h). The 20 bytes

contained in the device can then be accessed sequentially in the following order:

● 1st Byte: tenths/hundredths of a second register

● 2nd Byte: seconds register

● 3rd Byte: minutes register

● 4th Byte: century/hours register

● 5th Byte: day register

● 6th Byte: date register

● 7th Byte: month register

● 8th Byte: year register

● 9th Byte: control register

● 10th Byte: watchdog register

● 11th - 16th Bytes: alarm registers

● 17th - 19th Bytes: reserved

● 20th Byte: square wave register

The M41T81 clock continually monitors VCC for an out-of-tolerance condition. Should VCC

fall below VSO, the device terminates an access in progress and resets the device address

counter. Inputs to the device will not be recognized at this time to prevent erroneous data

from being written to the device from a an out-of-tolerance system. The device also

automatically switches over to the battery and powers down into an ultra low current mode

of operation to conserve battery life. As system power returns and VCC rises above VSO, the

battery is disconnected, and the power supply is switched to external VCC.

For more information on Battery Storage Life refer to Application Note AN1012.

2.1

2.1.1

2-wire bus characteristics

The bus is intended for communication between different ICs. It consists of two lines: a bi-

directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be

connected to a positive supply voltage via a pull-up resistor.

The following protocol has been defined:

● Data transfer may be initiated only when the bus is not busy.

● During data transfer, the data line must remain stable whenever the clock line is High.

● Changes in the data line, while the clock line is High, will be interpreted as control

signals.

Accordingly, the following bus conditions have been defined:

Bus not busy

Both data and clock lines remain High.

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