M41T81 查看數據表（PDF） - STMicroelectronics

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M41T81

Serial access real-time clock with alarm

STMicroelectronics 

M41T81

Figure 4. Serial bus data transfer sequence

DATA LINE

STABLE

DATA VALID

CLOCK

Operation

2.2

Note:

DATA

START

CONDITION

CHANGE OF

DATA ALLOWED

Figure 5. Acknowledgement sequence

START

SCL FROM

MASTER

1

2

DATA OUTPUT

BY TRANSMITTER

MSB

DATA OUTPUT

BY RECEIVER

STOP

CONDITION

AI00587

CLOCK PULSE FOR

ACKNOWLEDGEMENT

8

9

LSB

AI00601

READ mode

In this mode the master reads the M41T81 slave after setting the slave address (see

Figure 7 on page 10). Following the WRITE mode control bit (R/W=0) and the acknowledge

bit, the word address 'An' is written to the on-chip address pointer. Next the START condition

and slave address are repeated followed by the READ mode control bit (R/W=1). At this

point the master transmitter becomes the master receiver. The data byte which was

addressed will be transmitted and the master receiver will send an acknowledge bit to the

slave transmitter. The address pointer is only incremented on reception of an acknowledge

clock. The M41T81 slave transmitter will now place the data byte at address An+1 on the

bus, the master receiver reads and acknowledges the new byte and the address pointer is

incremented to “An+2.”

This cycle of reading consecutive addresses will continue until the master receiver sends a

STOP condition to the slave transmitter.

The system-to-user transfer of clock data will be halted whenever the address being read is

a clock address (00h to 07h). The update will resume due to a stop condition or when the

pointer increments to any non-clock address (08h-13h).

This is true both in READ mode and WRITE mode.

Doc ID 7529 Rev 10

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