M48T12(1998) 查看數據表（PDF） - STMicroelectronics
零件编号
产品描述 (功能)
生产厂家
M48T12 Datasheet PDF : 15 Pages
| |||
Figure 3. Block Diagram
M48T02, M48T12
32,768 Hz
CRYSTAL
LITHIUM
CELL
OSCILLATOR AND
CLOCK CHAIN
8 x 8 BiPORT
SRAM ARRAY
POWER
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
VPFD
BOK
2040 x 8
SRAM ARRAY
A0-A10
DQ0-DQ7
E
W
G
VCC
VSS
AI01329
Byte 7F8h is the clock control register. This byte
controls user access to the clock information and
also stores the clock calibration setting.
The eight clock bytes are not the actual clock
counters themselves; they are memory locations
consisting of BiPORT™ read/write memory cells.
The M48T02/12 includes a clock control circuit
which updates the clock bytes with current informa-
tion once per second. The information can be
accessed by the user in the same manner as any
other location in the static memory array.
The M48T02/12 also has its own Power-fail Detect
circuit. The control circuitry constantlymonitors the
single 5V supply for an out of tolerance condition.
When VCC is out of tolerance, the circuit write
protects the SRAM, providing a high degreeof data
security in the midst of unpredictable system op-
eration brought on by low VCC. As VCC falls below
approximately3V, the control circuitry connectsthe
battery which maintains data and clock operation
until valid power returns.
Table 4. AC Measurement Conditions
Input Rise and Fall Times
≤ 5ns
Input Pulse Voltages
0V to 3V
Input and Output Timing Ref. Voltages 1.5V
Note that Output Hi-Z is defined as the point where data is no
longer driven.
Figure 4. AC Testing Load Circuit
5V
DEVICE
UNDER
TEST
1kΩ
1.8kΩ
OUT
CL = 100pF
CL includes JIG capacitance
AI01019
3/15
Share Link: 