AD9432 查看數據表（PDF） - Analog Devices
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AD9432 Datasheet PDF : 16 Pages
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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD9432
52 51 50 49 48 47 46 45 44 43 42 41 40
GND 1
VCC 2
GND 3
GND 4
VCC 5
VCC 6
ENCODE 7
ENCODE 8
GND 9
VCC 10
GND 11
DGND 12
VDD 13
PIN 1
AD9432
TOP VIEW
(Not to Scale)
39 GND
38 GND
37 VCC
36 VCC
35 GND
34 GND
33 GND
32 VDD
31 DGND
30 D0 (LSB)
29 D1
28 D2
27 D3
14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43 42 41 40
GND 1
VCC 2
GND 3
GND 4
VCC 5
VCC 6
ENCODE 7
ENCODE 8
GND 9
VCC 10
GND 11
DGND 12
VDD 13
PIN 1
AD9432
TOP VIEW
(Not to Scale)
14 15 16 17 18 19 20 21 22 23 24 25 26
39 GND
38 GND
37 VCC
36 VCC
35 GND
34 GND
33 GND
32 VDD
31 DGND
30 D0 (LSB)
29 D1
28 D2
27 D3
NOTES
1. DNC = DO NOT CONNECT.
Figure 3. Pin Configuration, LQFP
NOTES
1. ALTHOUGH NOT REQUIRED IN ALL APPLICATIONS, THE EXPOSED PADDLE
ON THE UNDERSIDE OF THE PACKAGE SHOULD BE SOLDERED TO THE
GROUND PLANE. SOLDERING THE EXPOSED PADDLE TO THE PCB
INCREASES THE RELIABILITY OF THE SOLDER JOINTS, MAXIMIZING
THE THERMAL CAPABILITY OF THE PACKAGE.
Figure 4. Pin Configuration, TQFP_EP
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
1, 3, 4, 9, 11, 33,
34, 35, 38, 39, 40,
43, 48, 51
GND
2, 5, 6, 10, 36, 37, VCC
42, 44, 47, 52
7
ENCODE
8
ENCODE
12, 21, 24, 31
DGND
13, 22, 23, 32
VDD
14
OR
15 to 20, 25 to 30 D11 to D6, D5 to D0
41
DNC
45
VREFIN
46
VREFOUT
49
AIN
50
AIN
Exposed Pad
(TQFP_EP)
Description
Analog Ground.
Analog Supply (5 V).
Encode Clock for ADC, Complementary.
Encode Clock for ADC, True. ADC samples on rising edge of ENCODE.
Digital Output Ground.
Digital Output Power Supply (2.7 V to 3.6 V).
Out-of-Range Output.
Digital Output.
Do Not Connect.
Reference Input for ADC (2.5 V Typical). Bypass with 0.1 μF capacitor to ground.
Internal Reference Output (2.5 V Typical).
Analog Input, True.
Analog Input, Complementary.
Although not required in all applications, the exposed paddle on the underside of the TQFP_EP
package should be soldered to the ground plane. Soldering the exposed paddle to the PCB
increases the reliability of the solder joints, maximizing the thermal capability of the package.
Rev. F | Page 7 of 16
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