SN74LS163AMEL 查看數據表（PDF） - ON Semiconductor
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SN74LS163AMEL Datasheet PDF : 8 Pages
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SN74LS161A, SN74LS163A
AC CHARACTERISTICS (TA = 25°C)
Symbol
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
Parameter
Maximum Clock Frequency
Propagation Delay
Clock to TC
Propagation Delay
Clock to Q
Propagation Delay
CET to TC
MR or SR to Q
AC SETUP REQUIREMENTS (TA = 25°C)
Symbol
Parameter
tWCP
tW
ts
Clock Pulse Width Low
MR or SR Pulse Width
Setup Time, other*
ts
Setup Time PE or SR
th
Hold Time, data
th
Hold Time, other
trec
Recovery Time MR to CP
*CEP, CET, or DATA
Limits
Min Typ Max
25
32
20
35
18
35
13
24
18
27
9.0
14
9.0
14
20
28
Unit
MHz
ns
ns
ns
ns
Limits
Min Typ Max Unit
25
ns
20
ns
20
ns
25
ns
3
ns
0
ns
15
ns
Test Conditions
VCC = 5.0 V
CL = 15 pF
Test Conditions
VCC = 5.0 V
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to the clock transition from LOW to HIGH in
order to be recognized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time
following the clock transition from LOW to HIGH that the
logic level must be maintained at the input in order to ensure
continued recognition. A negative HOLD TIME indicates
that the correct logic level may be released prior to the clock
transition from LOW to HIGH and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW to HIGH in order to recognize and
transfer HIGH Data to the Q outputs.
AC WAVEFORMS
tW(H)
tW(L)
CP
1.3 V
tPHL
1.3 V
tPLH
Other conditions:
PE = MR (SR) = H
CEP = CET = H
Q
1.3 V
1.3 V
MR 1.3 V
CP
Q0 V Q1 V Q2 V Q3
tW
tPHL
trec
1.3 V
Other conditions:
PE = L
P0 = P1 = P2 = P3 = H
1.3 V
Figure 1. Clock to Output Delays, Count
Frequency, and Clock Pulse Width
Figure 2. Master Reset to Output Delay, Master Reset
Pulse Width, and Master Reset Recovery Time
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