DS1994 查看數據表（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS1994

4kb Plus Time Memory iButton

Dallas Semiconductor -> Maxim Integrated 

DS1994

Interval Timer

The interval timer is a 5-Byte binary counter. When enabled, it is incremented 256 times per second. The

least significant Byte is a count of fractional seconds. The interval timer can accumulate 136 years of

seconds before rolling over. The interval timer has two modes of operation that are selected by the

AUTO/MAN bit in the control register. In the auto mode, the interval timer begins counting after the data

line has been high for a period of time determined by the DSEL bit in the control register. Similarly, the

interval timer stops counting after the data line has been low for a period of time determined by the DSEL

bit. In the manual mode, time accumulation is controlled by the STOP/START bit in the control register.

NOTE: For auto mode operation, the high level on the data line must be greater than or equal to 2.1V.

Cycle Counter

The cycle counter is a 4-Byte binary counter. It increments after the falling edge of the data line if the

appropriate data line timing has been met. This timing is selected by the DSEL bit in the control register.

(See the Status/Control section).

NOTE: For cycle counter operation, the high level on the data line must be greater than or equal to 2.1V.

Alarm Registers

The alarm registers for the real-time clock, interval timer, and cycle counter all operate in the same

manner. When the value of a given counter equals the value in its associated alarm register, the

appropriate flag bit is set in the status register. If the corresponding interrupt enable bit in the status

register is set, an interrupt is generated. If a counter and its associated alarm register are write protected

when an alarm occurs, access to the device becomes limited. (See the Status/Control, Interrupts, and

Programmable Expiration sections.)

STATUS/CONTROL REGISTERS

The status and control registers are the first two Bytes of page 16 (see Figure 4).

Status Register

7

6

5

4

3

2

1

0

X

X CCE ITE RTE CCF ITF RTF 0200h

DON’T CARE BITS

READ ONLY

0 RTF Real-time clock alarm flag

1 ITF Interval timer alarm flag

2 CCF Cycle counter alarm flag

When a given alarm occurs, the corresponding alarm flag is set to a logic 1. The alarm flag is cleared by

reading the status register.

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