UT62L1024LCL-55LLI 查看數據表（PDF） - Utron Technology Inc
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UT62L1024LCL-55LLI Datasheet PDF : 14 Pages
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Rev. 1.1
UTRON
UT62L1024(I)
128K X 8 BIT LOW POWER CMOS SRAM
CAPACITANCE (TA=25℃, f=1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
CIN
CI/O
MIN.
-
-
MAX
6
8
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
UNIT
pF
pF
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0.1VCC to 0.9VCC
5ns
1.5V
CL = 30pF+1TTL, IOH= -1mA, IOL= 2.1mA
AC ELECTRICAL CHARACTERISTICS (VCC = 2.5V~3.6V, TA = - 40℃ to 85℃)
(1) READ CYCLE
PARAMETER
SYMBOL
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
tRC
tAA
tACE
tOE
tCLZ*
tOLZ*
tCHZ*
tOHZ*
tOH
UT62L1024(I)-55
MIN.
MAX.
55
-
-
55
-
55
-
30
10
-
5
-
-
20
-
20
10
-
UT62L1024(I)-70
MIN.
MAX.
70
-
-
70
-
70
-
35
10
-
5
-
-
25
-
25
10
-
(2) WRITE CYCLE
PARAMETER
SYMBOL
UT62L1024(I)-55
MIN.
MAX.
Write Cycle Time
tWC
55
-
Address Valid to End of Write
tAW
50
-
Chip Enable to End of Write
tCW
50
-
Address Set-up Time
tAS
0
-
Write Pulse Width
tWP
45
-
Write Recovery Time
tWR
0
-
Data to Write Time Overlap
tDW
25
-
Data Hold from End of Write Time
tDH
0
-
Output Active from End of Write
tOW*
5
-
Write to Output in High Z
tWHZ*
-
20
*These parameters are guaranteed by device characterization, but not production tested.
UT62L1024(I)-70
MIN.
MAX.
70
-
60
-
60
-
0
-
55
-
0
-
30
-
0
-
5
-
-
25
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
P80078
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