LC7074 查看數據表（PDF） - SANYO -> Panasonic

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LC7074

Synchronous Error Correction IC for RDS Applications

SANYO -> Panasonic 

2. Input Data Timing

LC7074, 7074M

• Input data is acquired on the falling edge of the input clock.

• Input data must be stable just before and just after the falling edge of the input clock. This means that it is desirable that

the input data change state on the rising edge of the input clock.

Input Data Timing

3. Serial Data Output Format and Timing

S

: Start bit (always “0”)

E

: Error flag } See table

F

: Correction flag

OE

: Offset E

OF

: Offset F (always “0” : reserved for future expansion)

A/B

: Group type version 0: Version A

1: Version B

E and F Flags

B1, B0 : Block number 00 : First block

E

F

D0 to D15 : RDS data

01 : Second block

10 : Third block

11 : Fourth block

No errors

Errors corrected

0

0

0

1

Uncorrectable errors

1

1

Note: When the CORR.SEL input pin is high level.

No.4789–9/17

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