8170FSZ 查看數據表（PDF） - Renesas Electronics
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产品描述 (功能)
生产厂家
8170FSZ
Renesas Electronics
8170FSZ Datasheet PDF : 14 Pages
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EL8170, EL8173
Input Bias Cancellation, Input
Bias Compensation
The EL8170 and EL8173 are features an Input Bias Cancellation
and Input Bias Compensation Circuit for both the input and
feedback terminals (IN+, IN-, FB+ and FB-), achieving a low input
bias current all throughout the input common-mode range and the
operating temperature range. While the PNP bipolar input stages
are biased with an adequate amount of biasing current for speed
and increased noise performance, the Input Bias Cancellation and
the Input Bias Compensation Circuit, sinks most of the base
current of the input transistor leaving a small portion as input bias
current, typically 500pA. In addition, the Input Bias Cancellation
and Input Bias Compensation Circuit, maintains a smooth and flat
behavior of the input bias current over the common mode range
and over the operating temperature range. The Input Bias
Cancellation and Input Bias Compensation Circuit, operates from
the input voltages of 10mV above the negative supply to the input
voltages slightly above the positive supply. See “Average Input Bias
Current vs Common-Mode Input Voltage” in the “Typical
Performance Curves” beginning on page 4.
Output Stage and Output Voltage Range
A pair of complementary MOSFET devices drives the output VOUT
to within a few millivolts of the supply rails. At a 100k load, the
PMOS sources current and pulls the output up to 4mV below the
positive supply, while the NMOS sinks current and pulls the
output down to 4mV above the negative supply, or ground in the
case of a single supply operation. The current sinking and
sourcing capability of the EL8170 and EL8173 are internally
limited to 26mA.
Gain Setting
VIN, the potential difference across IN+ and IN-, is replicated (less
the input offset voltage) across FB+ and FB-. The objective of the
EL8170 and EL8173 in-amp is to maintain the differential
voltage across FB+ and FB- equal to IN+ and IN-; (FB- - FB+) =
(IN+ - IN-). Consequently, the transfer function can be derived.
The gain of the EL8170 and EL8173 is set by two external
resistors, the feedback resistor RF, and the gain resistor RG.
VIN/2
VIN/2
VCM
+2.4V TO +5.5V
71
3 IN+
V+
+
2
8
IN- -
FB+ +
EL8170,
EL8173
6
5 FB- - V-
4
VOUT
RG
RF
VOUT
=
1
+
R-R----G-F--
VI
N
(EQ. 1)
In Figure 37, the FB+ pin and one end of resistor RG are connected
to GND. With this configuration, Equation 1 is only true for a positive
swing in VIN; negative input swings will be ignored and the output
will be at ground.
Reference Connection
Unlike a three op amp instrumentation amplifier, a finite series
resistance seen at the REF terminal does not degrade the
EL8170 and EL8173's high CMRR performance, eliminating the
need for an additional external buffer amplifier. The circuit shown
in Figure 38 uses the FB+ pin as a REF terminal to center or to
adjust the output. Because the FB+ pin is a high impedance
input, an economical resistor divider can be used to set the
voltage at the REF terminal. The reference voltage error due to
the input bias current is minimized by keeping the values of the
voltage divider resistors, R1 and R2, as low as possible. Any
voltage applied to the REF terminal will shift VOUT by VREF times
the closed loop gain, which is set by resistors RF and RG
according to Equation 2. Note that any noise or unwanted signals
on the reference supply will be amplified at the output according
to Equation 2.
VOUT
=
1
+
R-R----G-F--
VIN
+
1
+
R-R----G-F--
VREF
(EQ. 2)
+2.4V TO +5.5V
VIN/2
VIN/2
+2.4V TO +5.5V
VCM
R1
REF
R2 RG
71
3 IN+
V+
+
2 IN- - EL8170,
6
8 FB+ + EL8173
5 FB- - V-
4
RF
VOUT
FIGURE 38. GAIN SETTING AND REFERENCE CONNECTION
The FB+ pin can also be connected to the other end of resistor,
RG (see Figure 39). Keeping the basic concept that the EL8170
and EL8173 in-amps maintain constant differential voltage
across the input terminals and feedback terminals
(IN+ - IN- = FB+ - FB-), the transfer function of Figure 39 can be
derived (Equation 3). Note that the VREF gain term is eliminated,
and susceptibility to external noise is reduced.
FIGURE 37. GAIN IS SET BY TWO EXTERNAL RESISTORS, RF
AND RG
FN7490 Rev 8.00
August 11, 2015
Page 11 of 14
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