BA7630F 查看數據表（PDF） - ROHM Semiconductor

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BA7630F

Video switch for CANAL-Plus decoder

ROHM Semiconductor 

Multimedia ICs

•Digital circuit operation

(1) Introduction

The BA7630S has 9-bit serial-to-parallel converter and

latch circuit that has been included to expand the num-

ber of microprocessor output ports. The breakdown

voltage of the output pins is 13V, so switch them in the

range 0 to 12V. In addition to controlling the BA7630S

switching block, these outputs can be used to control

audio switching, scrambling decoders, and television

sets.

(2) Using the serial-to-parallel convertor block

Signal input is basically done using clock and date

pulses. As shown in Fig.10, the date is read on the ris-

ing edge of the clock pulses. If the date is “H” on the

rising edge of the clock pulse, a “L” data bit is input to

the shift register, and if the data is “L” on the rising

edge of the clock pulse, a “H” data bit is input to the

shift register. The shift register is sequentially incre-

mented by the bit corresponding to SW1. Data in

excess of 9 bits is sequentially discarded.

If the data is “H” on a falling edge of the clock, the con-

tents of the shift register are read into the internal latch,

and simultaneously output to the output port (the data

polarity is inverted on output). This output is maintained

until the latch is setup again.

To reset, set the RESET pin to “H”. The internal shift

register and latch contents go low (latch output all “H”),

for the duration that RESET is held high.

CLK

DATA

1

2

3

4

5

At points 1 to 4 data is input to the shift register.

At point 5 the contents of the shift register are transferred to the

latch and simultaneously output.

Fig. 4 CLK and DATA relationship

Data flow

Data in

1 2 3 4 5 6 7 8 9 Shift register

Latch

Reset

—

Q

—

Q

—

Q

—

Q

—

Q

—

Q

—

Q

—

Q

—

Q

Latch

SW1 SW2

SW9

Fig. 5 Digital block

BA7630S / BA7630F

(3) Pulse timing

The pulse timing diagrams are given below.

CLK

DATA

tsu

tsu

0.1µs (Typ.) 1.0µs (Max.)

Fig. 6 Clock rising edge and data relationship

(setup time)

CLK

DATA

tsu

tsu

0.1µs (Typ.) 1.0µs (Max.)

Fig. 7 Clock falling edge and data relationship

(setup time)

RESET

SW1 ~ SW9

OUT

tPLH tPHL

0.26µs (Typ.) 2.0µs (Max.)

Fig. 8 Reset and output relationship

(reset transmission time)

CLK

DATA

SW1 ~ SW9

OUT

tPLH9 tPHL

1.2µs (Typ.) 5.0µs (Max.)

Fig. 9 Clock falling edge and output relationship

(latch transmission time)

9

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