74F574PC(2000) 查看數據表（PDF） - Fairchild Semiconductor
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74F574PC Datasheet PDF : 7 Pages
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Unit Loading/Fan Out
Pin Names
D0–D7
CP
OE
O0–O7
Description
Data Inputs
Clock Pulse Input (Active LOW)
3-STATE Output Enable Input (Active LOW)
3-STATE Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
150/40 (33.3)
Input IIH/IIL
Output IOH/IOL
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
−3 mA/24 mA (20 mA)
Functional Description
The 74F574 consists of eight edge-triggered flip-flops with
individual D-type inputs and 3-STATE true outputs. The
buffered clock and buffered Output Enable are common to
all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold times
requirements on the LOW-to-HIGH Clock (CP) transition.
With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When OE is
HIGH, the outputs go to the high impedance state. Opera-
tion of the OE input does not affect the state of the flip-
flops.
Function Table
Inputs
Internal Outputs
OE CP D
Q
O
Function
HH L
NC
Z Hold
H
H
H
L
L
H
H
L
H
L
H
NC
L
H
L
H
Z Hold
Z Load
Z Load
L Data Available
H Data Available
LHL
NC
NC No Change in Data
L H H NC
NC No Change in Data
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
NC = No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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