UPA1764G 查看數據表（PDF） - NEC => Renesas Technology
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UPA1764G Datasheet PDF : 4 Pages
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DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ PA1764
SWITCHING
DUAL N-CHANNEL POWER MOS FET
INDUSTRIAL USE
DESCRIPTION
The µPA1764 is N-channel MOS Field Effect
Transistor designed for high current switching
applications.
FEATURES
• Dual chip type
• Low On-state Resistance
5 RDS(on)1 = 27 mΩ (TYP.) (VGS = 10 V, ID = 3.5 A)
5 RDS(on)2 = 32 mΩ (TYP.) (VGS = 4.5 V, ID = 3.5 A)
5 RDS(on)3 = 34 mΩ (TYP.) (VGS = 4.0 V, ID = 3.5 A)
• Low input capacitance
5 Ciss = 1300 pF (TYP.)
• Built-in G-S protection diode
• Small and surface mount package (Power SOP8)
ORDERING INFORMATION
PART NUMBER
PACKAGE
PACKAGE DRAWING (Unit : mm)
8
5
1 : Source 1
2 : Gate 1
7, 8 : Drain 1
3 : Source 2
4 : Gate 2
5, 6 : Drain 2
1
4
5.37 MAX.
6.0 ±0.3
4.4
0.8
1.27 0.78 MAX.
0.40
+0.10
–0.05
0.12 M
0.5 ±0.2
0.10
µPA1764G
Power SOP8
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.)
Drain to Source Voltage
VDSS
60
V
Gate to Source Voltage
VGSS
±20
V
Drain Current (DC)
Drain Current (pulse) Note1
Total Power Dissipation (1 unit) Note2
Total Power Dissipation (2 unit) Note2
ID(DC)
±7
A
ID(pulse)
±28
A
PT
1.7
W
PT
2.0
W
Channel Temperature
Tch
150
°C
Storage Temperature
Single Avalanche Current Note3
5 Single Avalanche Energy Note3
Tstg –55 to +150 °C
IAS
7
A
EAS
98
mJ
EQUIVALENT CIRCUIT
(1/2 circuit)
Drain
Gate
Body
Diode
Gate
Protection
Diode
Source
Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1 %
5
2. Mounted on ceramic substrate of 2000 mm2 x 2.2 mm
3. Starting Tch = 25 °C, RG = 25 Ω, VGS = 20 V → 0 V
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. G14329EJ1V0DS00 (1st edition)
Date Published January 2000 NS CP(K)
Printed in Japan
The mark 5 shows major revised points.
©
1999,2000
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