UPA1764G 查看數據表（PDF） - NEC => Renesas Technology
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UPA1764G Datasheet PDF : 4 Pages
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µ PA1764
5 ELECTRICAL CHARACTERISTICS (TA = 25 °C, All terminals are connected.)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN. TYP. MAX. UNIT
Drain to Source On-state Resistance
RDS(on)1 VGS = 10 V, ID = 3.5 A
27 35 mΩ
RDS(on)2 VGS = 4.5 V, ID = 3.5 A
32 42 mΩ
RDS(on)3 VGS = 4.0 V, ID = 3.5 A
34 46 mΩ
Gate to Source Cut-off Voltage
VGS(off) VDS = 10 V, ID = 1 mA
1.5 2.0 2.5 V
Forward Transfer Admittance
| yfs | VDS = 10 V, ID = 3.5 A
5.0 9.0
S
Drain Leakage Current
IDSS
VDS = 60 V, VGS = 0 V
10 µA
Gate to Source Leakage Current
IGSS
VGS = ±20 V, VDS = 0 V
±10 µA
Input Capacitance
Ciss
VDS = 10 V
1300
pF
Output Capacitance
Coss
VGS = 0 V
230
pF
Reverse Transfer Capacitance
Crss
f = 1 MHz
110
pF
Turn-on Delay Time
td(on)
ID = 3.5 A
15
ns
Rise Time
tr
VGS(on) = 10 V
69
ns
Turn-off Delay Time
td(off)
VDD = 30 V
65
ns
Fall Time
tf
RG = 10 Ω
27
ns
Total Gate Charge
QG
ID = 7.0 A
29
nC
Gate to Source Charge
QGS
VDD = 48 V
3.6
nC
Gate to Drain Charge
QGD
VGS = 10 V
7.4
nC
Body Diode Forward Voltage
VF(S-D) IF = 7.0 A, VGS = 0 V
0.84
V
Reverse Recovery Time
trr
IF = 7.0 A, VGS = 0 V
40
ns
Reverse Recovery Charge
Qrr
di/dt = 100 A / µs
66
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
L
PG.
50 Ω
VDD
VGS = 20 → 0 V
ID
VDD
IAS BVDSS
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
IG = 2 mA
RL
PG.
50 Ω
VDD
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG
PG.
VGS
0
τ
τ = 1 µs
Duty Cycle ≤ 1 %
RL
VGS
VGS
Wave Form
10 %
0
VGS(on) 90 %
VDD
ID
90 %
ID
ID
0 10 %
Wave Form
90 %
10 %
td(on) tr td(off) tf
ton
toff
2
Data Sheet G14329EJ1V0DS00
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