LH521028A 查看數據表（PDF） - Sharp Electronics
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LH521028A Datasheet PDF : 15 Pages
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CMOS 64K × 18 Static RAM
LH521028A
AC ELECTRICAL CHARACTERISTICS 1 (Over Operating Range)
SYMBOL
DESCRIPTION
–15
–17
–20
–25
–35
UNITS
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
READ CYCLE
tRC
Read Cycle Timing
15
17
20
25
35
ns
tAA
Address Access Time
15
17
20
25
35 ns
tASL
Address Setup to Latch Enable
2
2
2
2
2
ns
tAHL
Address Hold from Latch Enable
3
3
4
4
4
ns
tLEA
Latch Enable to Data Valid
16
18
21
26
36 ns
tLHM
Latch Enable High Pulse Width
5
5
5
5
5
ns
tOH
Output Hold from Address Change
4
4
4
4
4
ns
tLH
Output Hold from Latch High
4.5
4.5
4.5
4.5
4.5
ns
tEA
E Low to Valid Data
tELZ
E Low to Output Active 2,3
tEHZ
E High to Output High-Z 2,3
15
17
20
25
35 ns
3
3
3
3
3
ns
9
10
10
12
20 ns
tSA
S Low to Valid Data
tSLZ
S Low to Output Active 2,3
tSHZ
S High to Output High-Z 2,3
7
8
10
12
20 ns
2
2
2
3
3
ns
10
10
10
12
20 ns
tGA
G Low to Valid Data
tGLZ
G Low to Output Active 2,3
tGHZ
G High to Output High-Z 2,3
7
8
9
12
20 ns
0
0
0
0
0
ns
7
8
8
10
20 ns
tRCS
Read Setup from W High
0
0
0
0
0
ns
tRCH
tPU
tPD
Read Hold from W Low
E LOW to Power Up Time 3
E HIGH to Power Down Time 3
0
0
0
0
0
ns
0
0
0
0
0
ns
15
17
20
25
35 ns
tWA
Access Time From Write Enable HIGH
18
20
20
25
35 ns
WRITE CYCLE
tWC
Write Cycle Time
15
17
20
25
35
ns
tEW
E Low to End of Write
11
12
13
20
30
ns
tSW
S LOW to End of Write
7
8
10
20
30
ns
tAW
Address Valid to End of Write
11
12
13
20
30
ns
tAS
Address Setup to Start of Write
0
0
0
0
0
ns
tAH
Address Hold from End of Write
0
0
0
0
0
ns
tASL
Address Setup to Latch Enable
2
2
2
2
2
ns
tAHL
Address Hold from Latch Enable
3
3
4
4
4
ns
tLHW
Latch Hold from W High
0
0
0
0
0
ns
tLHM
Latch Enable HIGH Pulse Width
5
5
5
5
5
ns
tWP
W Pulse Width
11
12
13
20
30
ns
tDW
Input Data Setup Time
7
8
9
10
15
ns
tDH
tWHZ
tWLZ
Input Data Hold Time
W Low to Output High-Z 2,3
W High to Output Active 2,3
0
0
0
0
0
ns
7
8
8
10
14 ns
3
3
3
3
3
ns
NOTES:
1. AC Electrical Characteristics specified at ‘AC Test Conditions’ levels.
2. Active output to High-Z and High-Z to output active tests specified for a ±500 mV transition from steady state levels into the test load.
CLoad = 5 pF.
3. Guaranteed but not tested.
7
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