FM1608(2000) 查看數據表（PDF） - Ramtron International Corporation
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FM1608 Datasheet PDF : 12 Pages
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Ramtron
Figure 1. Block Diagram
Pin
A10-A12
Block Decoder
1Kx8
1Kx8
A0-A12
CE
Address
Latch
A0-A7
Row
Decoder
A8-A9
1Kx8
1Kx8
1Kx8
1Kx8
1Kx8
1Kx8
Column Decoder
FM1608
Description
WE
Control
Logic
OE
I/O Latch
Bus Driver
DQ0-7
Pin Name Pin Number
A0-A12 2-10, 21, 23-25
DQ0-7
/CE
11-13, 15-19
20
/OE
22
/WE
27
VDD
28
VSS
14
I/O Pin Description
I Address. The 13 address lines select one of 8,192 bytes in the FRAM
array. The address value will be latched on the falling edge of /CE.
I/O Data. 8-bit bi-directional data bus for accessing the FRAM array.
I Chip Enable. /CE selects the device when low. The falling edge of /CE
causes the address to be latched internally. Address changes that
occur after /CE goes low will be ignored until the next falling edge
occurs.
I Output Enable. When /OE is low the FM1608 drives the data bus when
valid data is available. Taking /OE high causes the DQ pins to be tri-
stated.
I Write Enable. Taking /WE low causes the FM1608 to write the contents
of the data bus to the address location latched by the falling edge of
/CE.
I Supply Voltage. 5V
I Ground.
Functional Truth Table
/CE
/WE
/OE
H
X
X
æ
X
X
L
H
L
L
L
X
Function
Standby/Precharge
Latch Address
Read
Write
28 July 2000
2/12
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