UPD4992CX 查看數據表（PDF） - NEC => Renesas Technology

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UPD4992CX

8-Bit Parallel I/O Calendar Clock

NEC => Renesas Technology 

µPD4992

MODE REGISTER (R/W)

HEX

0H

1H

2H

3H

4H

5H

6H

7H

8H

9H

AH

BH

CH

DH

EH

FH

BIN

0000B

0001B

0010B

0011B

0100B

0101B

0110B

0111B

1000B

1001B

1010B

1011B

1100B

1101B

1110B

1111B

Mode

Outputs TP2048 Hz

Outputs TP1024 Hz

Outputs TP256 Hz

Outputs TP64 Hz

Outputs INT1/2048s

Outputs INT1/1024s

Outputs INT1/256s

Outputs INT1/64s

Outputs INT1s

Outputs INT10s

Outputs INT60s

Outputs BUSY signal

Test mode 1

Test mode 2

Test mode 3

Test mode 4

CONTROL REGISTER

Access mode

When writing

When reading

b3

0

1

*

(Don’t care)

b2

b1

b0

CLK adjust

Reset

CLK stop

0: NOP

0: NOP

0: CLK start

––––––––––––––––––––––––––––––––––––––––––

1: CLK adjust

1: Reset

1: CLK stop

TP enable*1

INT reset

INT stop

0: TP = ENABLE

0: NOP

0: INT start

––––––––––––––––––––––––––––––––––––––––––

1: TP = DISABLE

1: Reset

1: INT stop

TP flag

OSC flag*2

BUSY flag*3

0: TP = Z

0: No oscillation

0: OFF

––––––––––––––––––––––––––––––––––––––––––

1: TP = L

1: Oscillation

1: ON

*1 : When TP enable is 1 (TP = DISABLE), the TP pin becomes high impedance (actually a high level because

a pull up resistor is connected to the TP pin).

But TP flag is not DISABLE in this case.

*2 : If the OSC flag becomes 0 by oscillation stop, the OSC flag remains to be 0 when oscillation is resumed.

To set OSC flag to 1 again, execute CLK reset (if the OSC flag still remains to be 0, oscillation has not been

started again).

Upon initial power application of the µPD4992, 0 is set to the OSC flag.

*3 : The BUSY flag is “1” when the time counter of the µPD4992 is operating (when read is disabled).

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