Q67000-A9210-A901 查看數據表（PDF） - Infineon Technologies

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Q67000-A9210-A901

5-V Low-Drop Fixed Voltage Regulator

Infineon Technologies 

TLE 4271

Application Description

The IC regulates an input voltage in the range of 5.5 V < VI < 36 V to VQnom = 5.0 V. Up

to 26 V it produces a regulated output current of more than 550 mA. Above 26 V the

save-operating-area protection allows operation up to 36 V with a regulated output

current of more than 300 mA. Overvoltage protection limits operation at 42 V. The

overvoltage protection hysteresis restores operation if the input voltage has dropped

below 36 V. The IC can be switched off via the inhibit input, which causes the quiescent

current to drop below 50 µA. A reset signal is generated for an output voltage of

VQ < 4.5 V. The watchdog circuit monitors a connected controller. If there is no positive-

going edge at the watchdog input within a fixed time, the reset output is set to low. The

delay for power-on reset and the maximum permitted watchdog-pulse period can be set

externally with a capacitor.

Design Notes for External Components

An input capacitor CI is necessary for compensation of line influences. The resonant

circuit consisting of lead inductance and input capacitance can be damped by a resistor

of approx. 1 Ω in series with CI. An output capacitor CQ is necessary for the stability of

the regulating circuit. Stability is guaranteed at values of CQ ≥ 22 µF and an ESR of

< 3 Ω.

Reset Circuitry

If the output voltage decreases below 4.5 V, an external capacitor CD on pin D will be

discharged by the reset generator. If the voltage on this capacitor drops below VDRL, a

reset signal is generated on pin RO, i.e. reset output is set low. If the output voltage rises

above the reset threshold, CD will be charged with constant current. After the power-on-

reset time the voltage on the capacitor reaches VDU and the reset output will be set high

again. The value of the power-on-reset time can be set within a wide range depending

of the capacitance of CD.

Reset Timing

The power-on reset delay time is defined by the charging time of an external capacitor

Cd which can be calculated as follows:

Cd = (td × Id)/∆V

Definitions:

Cd = delay capacitor

td = reset delay time

Id = charge current, typical 5 mA

∆V = VDU, typical 1.9 V

VDU = upper delay switching threshold at Cd for reset delay time

td = ∆V × CD/ID

Data Sheet Rev. 2.1

11

2000-02-14

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