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HS-24(1996) 查看數據表(PDF) - DATEL Data Acquisition products

零件编号
产品描述 (功能)
生产厂家
HS-24
(Rev.:1996)
Datel
DATEL Data Acquisition products  Datel
HS-24 Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
CDS-1402
®
®
ABSOLUTE MAXIMUM RATINGS
PHYSICAL/ENVIRONMENTAL
PARAMETERS
LIMITS
UNITS
PARAMETERS
MIN. TYP. MAX. UNITS
+5V Analog Supply (Pin 24)
0 to +6.3
Volts
–5V Analog Supply (Pin 13)
0 to –6.3
Volts
+5V Digital Supply (Pin 16)
–0.3 to +6
Volts
Digital Inputs (Pins 11, 12)
–0.3 to +VDD +0.3
Volts
Analog Inputs (Pins 3, 4)
±3.2
Volts
Lead Temperature (10 seconds)
+300
°C
Operating Temp. Range, Case
CDS-1402MC
CDS-1402MM
Thermal Impedance
θjc
θca
Storage Temperature Range
Package Type
Weight
FUNCTIONAL SPECIFICATIONS
(TA = +25°C, ±VCC = ±5V, +VDD = +5V, pixel rate = 5MHz, and a minimum warmup time of 2 minutes unless otherwise noted.)
+25°C
0 to +70°C
ANALOG INPUTS Œ
MIN.
TYP.
MAX.
MIN.
TYP. MAX.
0
+70
°C
–55
+125
°C
5
°C/W
22
°C/W
–65
+150
°C
24-pin, metal-sealed, ceramic DDIP
0.42 ounces(12 grams)
–55 to +125°C
MIN.
TYP. MAX.
UNITS
Input Voltage Range
Input Resistance
Input Capacitance
±2.5
±2.5
±2.5
Volts
500
500
500
Ohms
7
15
7
15
7
15
pF
DIGITAL INPUTS
Logic Levels
Logic "1"
Logic "0"
Logic Loading "1"
Logic Loading "0"
+2.0
+2.0
+2.0
Volts
+0.8
+0.8
+0.8
Volts
+10
+10
+10
µA
–10
–10
–10
µA
PERFORMANCE
Sample Mode Offset Error - S/H1
Gain Error - S/H1
Pedestal - S/H1
Sample Mode Offset Error - S/H2
Gain Error - S/H2
Pedestal - S/H2
Sample Mode Offset Error - CDS
Differential Gain Error - CDS
Pedestal - CDS
Pixel Rate (14-bit settling) 
Input Bandwidth, ±2.5V
Small Signal (–20dB input)
Large Signal (–0.5dB input)
Slew Rate
Aperture Delay Time
Aperture Uncertainty
S/H Acquisition Time Œ
(to ±0.01%, 5V step)
Hold Mode Settling Time
(to ±0.15mV)
Noise
Feedthrough Rejection
Overvoltage Recovery Time
S/H Saturation Voltage
Droop Rate
±3
±10
±4
±10
±5
±10
mV
±0.5
±1
±0.7
±1
±0.75
±1
%
±5
±25
±10
±25
±15
±25
mV
±3
±10
±4
±10
±5
±10
mV
±0.5
±1
±0.7
±1
±0.75
±1
%
±5
±25
±10
±25
±15
±25
mV
±3
±10
±4
±10
±5
±10
mV
±0.5
±1.5
±0.5
±1.5
±0.75
±1.5
%
±10
±25
±10
±25
±15
±30
mV
5
5
5
MSPS
24
8
±500
10
5
24
8
±500
10
5
24
MHz
8
MHz
±500
V/µs
10
ns
5
ps rms
50
100
60
100
75
100
ns
20
20
20
ns
200
200
200
µVrms
72
72
72
dB
200
200
200
ns
±3.2
±3.2
±3.2
V
±10
±25
±10
±25
±15
±25
mV/µs
ANALOG OUTPUTS Ž
Output Voltage Range
Output Impedance
Output Current
±2.5
±2.5
±2.5
Volts
0.5
0.5
0.5
Ohms
±20
±20
±20
mA
DIGITAL OUTPUTS
Logic Levels
Logic "1"
Logic "0"
Logic Loading "1"
Logic Loading "0"
+3.9
+3.9
+3.9
Volts
+0.4
+0.4
+0.4
Volts
–4
–4
–4
mA
+4
+4
+4
mA
Œ Pins 3 and 4.  See Figure 4 for relationship between input voltage, accuracy, and acquisition time. Ž Pins 6 and 22.
2

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