514MLF 查看數據表（PDF） - Integrated Device Technology
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514MLF Datasheet PDF : 7 Pages
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ICS514
LOCO™ PLL CLOCK GENERATOR
CLOCK MULTIPLIER
Pin Assignment
X1/ICLK 1
VDD 2
GND 3
REF 4
8 X2
7 S1
6 S0
5 CLK
8-pi n (150 mi l ) SOI C
Clock Decoding Table (MHz) with 14.31818
MHz Crystal or Clock Input
S1 S0
CLK
0 0 Power-down CLK
01
25
M0
33.33
M1
40
10
50
11
66.66
Multiplier
—
1.746
2.328
2.794
3.492
4.656
Accuracy
—
1 ppm
0.008%
1 ppm
1 ppm
0.008%
0 = connect directly to ground
1 = connect directly to VDD
M = leave unconnected (floating)
CLK and REF stop low in power-down state
Pin Descriptions
Pin
Pin
Number Name
1
XI/ICLK
2
VDD
3
GND
4
REF
5
CLK
6
S0
7
S1
8
X2
Pin
Type
Input
Power
Power
Output
Output
Tri-level Input
Tri-level Input
Output
Pin Description
Crystal connection to a 14.31818 MHz crystal or clock input.
Connect to +3.3 V or +5 V.
Connect to ground.
Reference 14.31818 MHz crystal oscillator buffered clock output.
Clock output per table above.
Select 0 for output clock. Connect to GND or VDD or float. See
table above.
Select 1 for output clock. Connect to GND or VDD or float. See
table above.
Crystal connection to a 14.31818 MHz crystal. Leave unconnected
for clock input.
Notes:
1. With S1 = S0 = 0, the internal PLL is turned off and the CLK outputs stops low. The crystal oscillator and
REF output are still active.
2. With a clock input, the phase relationship between the input and the output clocks can change each time
the device is powered on. If a fixed phase relationship is required, use the ICS571 or other zero delay
multipliers.
IDT™ / ICS™ LOCO™ PLL CLOCK GENERATOR
2
ICS514
REV G 051310
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