ML6692 查看數據表（PDF） - Micro Linear Corporation

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ML6692

100BASE-TX Physical Layer with MII

Micro Linear Corporation 

ML6692

PIN DESCRIPTION (Pin Numbers for TQFP package in parentheses)

PIN

NAME

FUNCTION

1 (56)

TXCLKIN

Transmit clock TTL input. This 25MHz clock is the frequency reference for the internal

transmit PLL clock multiplier. This pin should be driven by an external 25MHz clock at

TTL or CMOS levels.

2 (57, 58)

AGND1

Analog ground.

3, 4, 5, 6,

TXD<3:0> Transmit data TTL inputs. TXD<3:0> inputs accept TX data from the MII. Data

(59, 60, 61, 62)

appearing at TXD<3:0> are clocked into the ML6692 on the rising edge of TXCLK.

7 (63)

TXEN

Transmit enable TTL input. Driving this input high indicates to the ML6692 that transmit

data are present at TXD<3:0>. TXEN edges should be synchronous with TXCLK.

8 (64)

TXER

Transmit error TTL input. Driving this pin high with TXEN also high causes the part to

continuously transmit scrambled H symbols. When TXEN is low, TXER has no effect.

9 (1)

TXCLK

Transmit clock TTL output. This 25MHz clock is phase-aligned with the internal 125MHz

TX bit clock. Data appearing at TXD<3:0> are clocked into the ML6692 on the rising

edge of this clock.

10, 12, 14, 16 RXD<3:0> Receive data TTL outputs. RXD<3:0> outputs are valid on RXCLK’s rising edge.

(2, 5, 8, 11)

11 (3, 4)

DGND1 Digital ground.

13 (6, 7)

DVCC1

Digital +5V power supply.

15 (9, 10)

17 (12)

18 (13)

19 (14)

20 (15, 16)

21 (17)

22 (18)

23 (19)

24 (20)

DGND2

RXCLK

CRS

COL

DGND3

RXDV

DVCC2

RXER

MDC

Digital ground.

Recovered receive clock TTL output. This 25MHz clock is phase-aligned with the

internal 125MHz bit clock recovered from the signal received at TPINP/N. Receive data

at RXD<3:0> changes on the falling edges and should be sampled on the rising edges of

this clock. RXCLK is phase aligned to TXCLKIN when the 100BASE-TX signal is not

present at TPINP/N.

Carrier Sense TTL output. For 100Mbps operation in standard mode, CRS goes high in the

presennon-idle signals at TPINP/N, or when the ML6692 is transmitting. CRS goes low when

there is no transmit activity and receive is idle. For 100 Mbps operation in repeater mode

or half duplex mode, CRS goes high in the presence of non-idle signals at TPINP/N only.

Collision Detected TTL output. For 100 Mbps operation COL goes high upon detection of

a collision on the network, and remains high as long as the collision condition persists.

COL is low when the ML6692 operates in either full duplex, or loopback modes.

Digital ground.

Receive data valid TTL output. This output goes high when the ML6692 is receiving a

data packet. RXDV should be sampled synchronously with RXCLK’s rising edge.

Digital +5V power supply.

Receive error TTL output. This output goes high to indicate error or invalid symbols

within a packet, or corrupted idle between packets. RXER should be sampled

synchronously with RXCLK’s rising edge.

MII Management Interface clock TTL input. A clock at this pin clocks serial data into or

out of the ML6692’s MII management registers through the MDIO pin. The maximum clock

frequency at MDC is 2.5MHz.

4

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