IDT54FCT88915TT100L 查看數據表（PDF） - Integrated Device Technology

零件编号

产品描述 (功能)

生产厂家

IDT54FCT88915TT100L

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

Integrated Device Technology 

IDT54/74FCT88915TT 55/70/100/133

LOW SKEW PLL-BASED CMOS CLOCK DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

NOTES:

7. These two specs ( tRISE/FALL and tPULSE WIDTH 2Q output) guarantee that the FCT88915TT meets 68040 P-Clock input specification.

88915TT

2Q

Output

Zo (clock trace)

Rp

68040

P-Clock

Input

Rp = 1.5 Zo

3072 drw 04

8. The wiring diagrams and written explanations of Figure 4 demonstrate the input and output frequency relationships for various possible feedback

configurations. The allowable SYNC input range to stay in the phase-locked condition is also indicated. There are two allowable SYNC frequency ranges,

depending on whether FREQ_SEL is HIGH or LOW. Also it is possible to feed back the Q5 output, thus creating a 180° phase shift between the SYNC

input and the Q outputs. The table below summarizes the allowable SYNC frequency range for each possible configuration.

FREQ_SEL

Level

HIGH

Feedback

Output

Q/2

Allowable SYNC Input

Frequency Range (MHZ)

10 to (2Q fMAX Spec)/4

Corresponding 2Q output

Frequency Range

40 to (2Q fMAX Spec)

Phase Relationship

of the Q Outputs

to Rising SYNC Edge

0°

HIGH

Any Q (Q0-Q4)

20 to (2Q fMAX Spec)/2

40 to (2Q fMAX Spec)

0°

HIGH

Q5

20 to (2Q fMAX Spec)/2

40 to (2Q fMAX Spec)

180°

HIGH

2Q

40 to (2Q fMAX Spec)

40 to (2Q fMAX Spec)

0°

LOW

Q/2

5 to (2Q fMAX Spec)/8

20 to (2Q fMAX Spec)/2

0°

LOW

Any Q (Q0-Q4)

10 to (2Q fMAX Spec)/4

20 to (2Q fMAX Spec)/2

0°

LOW

Q5

10 to (2Q fMAX Spec)/4

20 to (2Q fMAX Spec)/2

180°

LOW

2Q

20 to (2Q fMAX Spec)/2

20 to (2Q fMAX Spec)/2

0°

3072 tbl 09

9. The tPD spec describes how the phase offset between the SYNC input and the output connected to the FEEDBACK input, varies with process, temperature

and voltage. Measurements were made with a 10MHz SYNC input and Q/2 output as feedback. The phase measurements were made at 1.5V.

The Q/2 output was terminated at the FEEDBACK input with 100Ω to VCC and 100Ω to ground.

tPD measurements were made with the loop filter connection shown below:

External Loop

Filter

LF

0.1µF

C1

Analog GND

3072 drw 05

9.7

6

Share Link: