W77E468 查看數據表（PDF） - Winbond
零件编号
产品描述 (功能)
生产厂家
W77E468 Datasheet PDF : 84 Pages
| |||
Preliminary W77E468
SLAVE ADDRESS MASK ENABLE
Bit:
7
6
5
4
3
2
1
0
Mnemonic: SADEN
Address: B9h
SADEN: This register enables the Automatic Address Recognition feature of the Serial port 0. When
a bit in the SADEN is set to 1, the same bit location in SADDR will be compared with the
incoming serial data. When SADEN.n is 0, then the bit becomes a "don't care" in the
comparison. This register enables the Automatic Address Recognition feature of the Serial
port 0. When all the bits of SADEN are 0, interrupt will occur for any incoming address.
SLAVE ADDRESS MASK ENABLE 1
Bit:
7
6
5
4
3
2
1
0
Mnemonic: SADEN1
Address: BAh
SADEN1:This register enables the Automatic Address Recognition feature of the Serial port 1. When
a bit in the SADEN1 is set to 1, the same bit location in SADDR1 will be compared with the
incoming serial data. When SADEN1.n is 0, then the bit becomes a "don't care" in the
comparison. This register enables the Automatic Address Recognition feature of the Serial
port 1. When all the bits of SADEN1 are 0, interrupt will occur for any incoming address.
SERIAL PORT CONTROL 1
Bit:
7
6
SM0_1/FE_1 SM1_1
5
4
SM2_1 REN_1
3
TB8_1
2
RB8_1
1
TI_1
0
RI_1
Mnemonic: SCON1
Address: C0h
SM0_1/FE_1: Serial port 1, Mode 0 bit or Framing Error Flag 1: The SMOD0 bit in PCON SFR
determines whether this bit acts as SM0_1 or as FE_1. the operation of SM0_1 is
described below. When used as FE_1, this bit will be set to indicate an invalid stop bit.
This bit must be manually cleared in software to clear the FE_1 condition.
SM1_1: Serial port 1 Mode bit 1:
SM0_1
0
0
1
1
SM1_1
0
1
0
1
Mode
0
1
2
3
Description
Synchronous
Asynchronous
Asynchronous
Asynchronous
Length
8
10
11
11
Baud rate
4/12 Tclk
variable
64/32 Tclk
variable
- 22 -
Share Link: 