ISL8201M 查看數據表（PDF） - Renesas Electronics
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ISL8201M Datasheet PDF : 16 Pages
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ISL8201M
VOUT
500mV/DIV
FIGURE 18. PRE-BIASED START-UP - OVERCHARGED
If the VIN for the synchronous buck converter is from a different
supply that comes up after PVCC, the soft-start will go through
its cycle, but with no output voltage ramp. When VIN turns on,
the output will follow the ramp of the VIN from zero up to the
final expected voltage (at close to 100% duty cycle, with
COMP/EN pin >4V). If VIN is too fast, there may be excessive
in-rush current charging the output capacitors (only the
beginning of the ramp, from zero to VOUT matters here). If this
is not acceptable, then consider changing the sequencing of
the power supplies, sharing the same supply, or adding
sequencing logic to the COMP/EN pin to delay the soft-start
until the VIN supply is ready (see “Input Voltage
Considerations” on page 11).
If ISL8201M is disabled after soft-start (by pulling COMP/EN
pin low), and afterwards enabled (by releasing the COMP/EN
pin), then the full initialization (including OCP sample) will take
place. However, there is no new OCP sampling during
overcurrent retries. If the output is shorted to GND during soft-
start, the OCP will handle it, as described in the next section.
Overcurrent Protection (OCP)
The overcurrent function protects the converter from a shorted
output by using the low-side MOSFET ON-resistance, rDS(ON),
to monitor the current. A resistor (RSET) programs the
overcurrent trip level.
This method enhances the converter's efficiency and reduces
cost by eliminating a current sensing resistor. If overcurrent is
detected, the output immediately shuts off. It cycles the soft-
start function in a hiccup mode (2 dummy soft-start time-outs,
then up to one real one) to provide fault protection. If the
shorted condition is not removed, this cycle will continue
indefinitely.
Following POR (and 6.8ms delay), the ISL8201M initiates the
overcurrent protection sample and hold operation. The low-
side gate driver is disabled to allow an internal 21.5µA current
source to develop a voltage across RSET. The ISL8201M
samples this voltage (which is referenced to the PGND pin) at
the ISET pin, and holds it in a counter and DAC combination.
This sampled voltage is held internally as the overcurrent set
point, for as long as power is applied, or until a new sample is
taken after coming out of a shut-down.
The actual monitoring of the low-side MOSFET ON-resistance
starts 200ns (nominal) after the edge of the internal PWM logic
signal (that creates the rising external low-side gate signal).
This is done to allow the gate transition noise and ringing on
the PHASE pin to settle out before monitoring. The monitoring
ends when the internal PWM edge (and thus low-side gate
signal) goes low. The OCP can be detected anywhere within
the above window.
If the converter is running at high duty cycles around 75% for
600kHz operation, then the low-side gate pulse width may not
be wide enough for the OCP to properly sample the rDS(ON).
For those cases, if the low-side gate signal is too narrow (or
not there at all) for 3 consecutive pulses, then the third pulse
will be stretched and/or inserted to the 425ns minimum width.
This allows for OCP monitoring every third pulse under this
condition. This can introduce a small pulse-width error on the
output voltage, which will be corrected on the next pulse; and
the output ripple voltage will have an unusual 3-clock pattern,
which may look like jitter.
The overcurrent function will trip at a peak inductor current
(IPEAK) determined by Equation 2:
IPEAK = 2----------I-r-S--D--E--S--T----O----N-R-----S----E----T-
(EQ. 2)
where:
ISET is the internal ISET current source (21.5µA typical).
RSET is equivalent resistance between ISET and PGND pins.
rDS(ON) is typically 6.1m at (VPVCC = VGS = 10V, IDS = 30A)
and 9m at (VPVCC = VGS = 4.5V, IDS = 30A).
Note: ISL8201M has integrated 3.57k resistance (RSET-IN).
Therefore, the equivalent resistance of RSET can be expressed
in Equation 3:
RSET = -RR----SS----EE----TT--------EE----XX-----+----RR-----SS----EE----TT-------I-I-NN---
(EQ. 3)
The scale factor of 2 doubles the trip point of the MOSFET
voltage drop, compared to the setting on the RSET resistor. The
OC trip point varies in a system mainly due to the MOSFET
rDS(ON) variations (i.e. over process, current and temperature).
To avoid overcurrent tripping in the normal operating load
range, find the RSET resistor from Equation 4, and with Steps 1
to 3:
1. The maximum rDS(ON) at the highest junction temperature
2. The minimum ISET from the “Electrical Specifications” table
on page 3.
FN6657 Rev 3.00
October 28, 2014
Page 10 of 16
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