MPC2105A 查看數據表（PDF） - Motorola => Freescale
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MPC2105A
Motorola => Freescale
MPC2105A Datasheet PDF : 20 Pages
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DATA RAM MCM69F618A SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3)
STANDBY ADSx
CNTENx CWEx
CLKx
Address Used
Operation
H
L
X
X
L–H
N/A
Deselected
L
L
X
L
L–H
External Address
Write Cycle, Begin Burst
L
L
X
H
L–H
External Address
Read Cycle, Begin Burst
X
H
L
L
L–H
Next Address
Write Cycle, Continue Burst
X
H
L
H
L–H
Next Address
Read Cycle, Continue Burst
X
H
H
L
L–H
Current Address
Write Cycle, Suspend Burst
X
H
H
H
L–H
Current Address
Read Cycle, Suspend Burst
NOTES:
1. X means Don’t Care.
2. All inputs except CG must meet set–up and hold times for the low–to–high transition of clock (CLK0 – CLK4).
3. Wait states are inserted by suspending burst.
ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)
Operation
CG
I/O Status
Read
L
Data Out (DQ0 – DQ8)
Read
H
High–Z
Write
X
High–Z — Data In
Deselected
X
High–Z
NOTES:
1. X means Don’t Care.
2. For a write operation following a read operation, CG must be high before the input data
required set–up time and held high through the input data hold time.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V)
Rating
Symbol
Value
Unit
Power Supply Voltage
VCC
– 0.5 to + 7.0
V
Voltage Relative to VSS
Vin, Vout – 0.5 to VCC + 0.5 V
Output Current (per I/O)
Data RAM Iout
Tag
± 30
mA
± 20
Power Dissipation
MPC2105A/B PD
MPC2106A/B
4.6
W
9.2
Temperature Under Bias
Tbias
– 10 to + 85
°C
Operating Temperature
TA
0 to +70
°C
Storage Temperature
Tstg
– 55 to + 125
°C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
This device contains circuitry that will
ensure the output devices are in High–Z at
power up.
MPC2105A•MPC2106A•MPC2105B•MPC2106B
6
MOTOROLA FAST SRAM
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