MB15F07SL 查看數據表（PDF） - Fujitsu
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MB15F07SL Datasheet PDF : 27 Pages
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MB15F07SL
Table 8. LD/fout Output Select Data Setting
LDS
H
L
LD/fout output signal
fout (fr1/fr2, fp1/fp2) signals
LD signal
Table 9. Charge Pump Current Setting
CS
Current value
H
±6.0 mA
L
±1.5 mA
Power Saving Mode (Intermittent Mode Control Circuit)
Table 10. PS Pin Setting
PS pin
H
L
Status
Normal mode
Power saving mode
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See
the Electrical Characteristics chart for the specific value.
The phase detector output, Do, becomes high impedance.
For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table.
Setting the PS pin high, releases the power saving mode, and the device works normally.
The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because
of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can
cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in lockup time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error signal
from the phase detector when it returns to normal operation.
Notes: •When power (VCC) is first applied, the device must be in standby mode, PS = Low, for at least 1 µs.
•PS pins must be set at “L” for Power-ON.
OFF
ON
VCC
tv ≥ 1 µs
Clock
Data
,,,,,,,,,,,,,,
LE
tps ≥ 100 ns
PS
(1)
(2)
(3)
(1) PS = L (power saving mode) at Power-ON
(2) Set serial data 1 µs later after power supply remains stable (VCC > 2.2 V).
(3) Release power saving mode (PS: “L” → “H”) 100 ns later after setting serial data.
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